Explore topic-wise MCQs in Vlsi.

This section includes 25 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.

1.

In BiCMOS driver, a good bipolar transistor should have ___________

A. low Rc
B. high hfe
C. high gm
D. all of the mentioned
Answer» E.
2.

Which has a larger value?

A. Tin
B. TL
C. Rc
D. None of the mentioned
Answer» B. TL
3.

In BiCMOS drivers, the input voltage Vbe is _______ on base width.

A. directly proportional
B. inversely proportional
C. logarithmically proportional
D. exponentially proportional
Answer» D. exponentially proportional
4.

When number of stages N is even, the total delay for CMOS can be?

A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer» D. 4.5NfƮ
5.

When number of stages N is even, the total delay for nMOS can be?

A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer» C. 3.5NfƮ
6.

The number of stages N can be given as ___________

A. ln(y)*ln(f)
B. ln(y)/ln(f)
C. ln(f)/ln(y)
D. ln(f)/ln(2y)
Answer» C. ln(f)/ln(y)
7.

What is the total delay of a CMOS pair?

A. 5fƮ
B. 7fƮ
C. 8fƮ
D. 4fƮ
Answer» C. 8fƮ
8.

What is the total delay of an nMOS pair?

A.
B. 2fƮ
C. 5fƮ
D. 4fƮ
Answer» D. 4fƮ
9.

Delay per stage for logic 1 to 0 transition can be given as __________

A.
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer» E.
10.

Delay per stage for logic 0 to 1 transition can be given as __________

A.
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer» B. 2fƮ
11.

As width increases, capacitive load __________

A. increases
B. decreases
C. does not change
D. exponentially increases
Answer» B. decreases
12.

To reduce resistance value of inverters, channels must be made __________

A. wider
B. narrower
C. lenghthier
D. shorter
Answer» B. narrower
13.

For shorter delays ______ resistance should be used.

A. smaller
B. larger
C. does not depend on resistance
D. very large
Answer» B. larger
14.

WHEN_NUMBER_OF_STAGES_N_IS_EVEN,_THE_TOTAL_DELAY_FOR_CMOS_CAN_BE_GIVEN_AS?$

A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer» D. 4.5Nf‚Äö√†√ú‚àö√ú
15.

Which has larger value?$

A. Tin
B. TL
C. Rc
D. None of the mentioned
Answer» B. TL
16.

In BiCMOS drivers, the input voltage Vbe is _______ on base width$

A. directly proportional
B. inversely proportional
C. logarithmically proportional
D. exponentially proportional
Answer» D. exponentially proportional
17.

In BiCMOS driver, a good bipolar transistor should have

A. low Rc
B. high hfe
C. high gm
D. all of the mentioned
Answer» E.
18.

When number of stages N is even, the total delay for nMOS can be given a?

A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer» C. 3.5Nf‚Äö√†√ú‚àö√ú
19.

The number of stages N can be given as

A. ln(y)*ln(f)
B. ln(y)/ln(f)
C. ln(f)/ln(y)
D. ln(f)/ln(2y)
Answer» C. ln(f)/ln(y)
20.

Total delay of an nMOS pair is

A. fƮ
B. 2fƮ
C. 5fƮ
D. 4fƮ
Answer» D. 4f‚Äö√†√ú‚àö√ú
21.

Delay per stage for logic 1 to 0 transition can be given as

A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer» E.
22.

Delay per stage for logic 0 to 1 transition can be given as

A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer» B. 2f‚Äö√†√ú‚àö√ú
23.

As width increases, capacitive load

A. increases
B. decreases
C. does not change
D. exponentially increases
Answer» B. decreases
24.

To reduce resistance value of inverters, channels must be made

A. wider
B. narrower
C. lenghthier
D. shorter
Answer» B. narrower
25.

For shorter delays ______ resistance should be used

A. smaller
B. larger
C. does not depend on resistance
D. very large
Answer» B. larger