Explore topic-wise MCQs in Engineering.

A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.

The process of reduction or simplification of combinational logic circuits increases the cost of the circuit.

The Boolean equation ________ results from this Karnaugh map.

The addition of two signed numbers in the 2's complement system can cause overflow. For overflow to occur both numbers must ________.

Parity generators and checkers use ________ gates.

The 7447A is a BCD-to-7-segment decoder with ripple blanking input and output functions. The purpose of these lines is to ________.

When an open occurs on the input of a CMOS gate, the output will ________.

To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is ________.

The K-map provides a "graphical" approach to simplifying sum-of-products expressions.

A pull-up resistor is a resistor used to keep a given point in a circuit HIGH when in the active state.

In an even-parity system, the following data will produce a parity bit = 1.
data = 1010011

The Boolean equation results from this Karnaugh map.

The following combination is correct for an ODD parity data transmission system:
data = 011011100 and parity = 0

Even parity is the condition of having an even number of 1s in every group of bits.

The look-ahead carry method suffers from propagation delays.

The Boolean equation results from this Karnaugh map.

The standard SOP form of the expression is ________.

Identify the Boolean expression that is in standard POS form.

A combinatorial logic circuit has memory characteristics that "remember" the inputs after they have been removed.

In a typical digital system, Logic 0 is 0V 0.8V, and Logic 1 is ________.

The rise-time of a pulse is normally measured between the ________.

The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.

A logic circuit that can store one bit of information is a ________.

Modulus refers to ________.

In VHDL, when we want to remember a value it must be stored in a VARIABLE.

In a seven-segment LED display, the BCD must be decoded into a format that can be used to drive the decimal numeric display.

Parallel in/parallel out registers have parallel input and output busses.

Once an up/down counter begins its count sequence, it cannot be reversed.

A BCD counter has ________ states.

The technique used by one-shots to respond to an edge rather than a level is called ________.

The circuit shown below is a ________.

A sequential circuit design is used to ________.

The MOD-10 counter is also referred to as a ________ counter.

In general, when using a scope to troubleshoot digital systems the instrument should be triggered by ________.

________ is the modulus of the counter shown below.

________ counters are often used whenever pulses are to be counted and the results displayed in decimal.

A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.

Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way.

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________.

________ is the output frequency of the counter shown below.

In order to use a shift register as a counter, ________.

A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________.

Referring to the function table given below, taking the CLEAR, S1, and S0 inputs all HIGH ________.

Assume a 4-bit ripple counter has a failure in the second flip-flop such that it "locks up." The third and fourth stages will ________.

The circuit shown below is a ________.

Assume you want to determine the timing diagram for a 4-bit counter using an oscilloscope. The best choice for an oscilloscope trigger signal is ________.

It is a characteristic of ring counters that the ________ equal to the number of flip-flops in the register.

Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting.