MCQOPTIONS
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MCQOPTIONS
This section includes 102 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Architecture knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Asynchronous inputs, just like synchronous inputs, can be engineered to be ______________. |
| A. | Active-Medium |
| B. | Active-Low |
| C. | Active-High |
| D. | Both b and c |
| Answer» E. | |
| 2. |
The characteristic equation of any flip-flop describes the __________________ of the next state in terms of the present state and inputs. |
| A. | Impact |
| B. | Behavior |
| C. | Path |
| D. | None of the above |
| Answer» C. Path | |
| 3. |
___________ and Clear should not be 0 at the same time; otherwise, both the outputs will be 1, which is known as invalid state. |
| A. | Preset |
| B. | Post set |
| C. | Fixed |
| D. | Both a and b |
| Answer» B. Post set | |
| 4. |
When a circuit is self- correcting? |
| A. | If there are N-1 cycles among its unused states |
| B. | If there are N-1 cycles among its used states |
| C. | If there are no cycles among its used states |
| D. | If there are no cycles among its unused states |
| Answer» E. | |
| 5. |
This converter deals with converting binary code to gray code |
| A. | Binary to Gray Code Converter |
| B. | Gray to Binary Code Converter |
| C. | Binary Code Converter |
| D. | Gray Code Converter |
| Answer» B. Gray to Binary Code Converter | |
| 6. |
It is a circuit, which can remember values for a long time or change values when required. |
| A. | Ripple |
| B. | Counter |
| C. | Circuit |
| D. | Memory Element |
| Answer» E. | |
| 7. |
It is a bi-directional counter capable of counting in either of the direction depending on the control signal |
| A. | Up Synchronous Counter |
| B. | Down Synchronous Counter |
| C. | Synchronous Counter |
| D. | Both a and b |
| Answer» E. | |
| 8. |
When more than one input can be active, the priority ____________ must be used. |
| A. | Terms |
| B. | Words |
| C. | Encoder |
| D. | None of the above |
| Answer» D. None of the above | |
| 9. |
A device that exhibits two different stable states and functions as a memory element in a binary system is known as______________________ . |
| A. | Registers |
| B. | Flip-Flop |
| C. | VLSI |
| D. | Both b and c |
| Answer» C. VLSI | |
| 10. |
A combinational logic circuit which sends data coming from a single source to two or more separate destinations is |
| A. | Decoder |
| B. | Encoder |
| C. | Multiplexer |
| D. | Demultiplexer |
| Answer» E. | |
| 11. |
It compares two n-bit values to determine whether one of them is greater or if they are equal. |
| A. | Calculator |
| B. | Multiplexer |
| C. | Comparator |
| D. | None of the above |
| Answer» D. None of the above | |
| 12. |
The different types of flip-flops are_____, __________ and____________. |
| A. | R-S |
| B. | D, T |
| C. | J-K |
| D. | All of the above |
| Answer» E. | |
| 13. |
In ________________ circuit, the output depends on both the present and the past inputs. |
| A. | Parallel |
| B. | Sequential |
| C. | Combinational |
| D. | None of the above |
| Answer» D. None of the above | |
| 14. |
In this type of counter, the complement of the output of the last stage of the shift register is fed back to the D input of the first state. |
| A. | Ring Counter |
| B. | Johnson Counter |
| C. | Straight Counter |
| D. | None of the above |
| Answer» C. Straight Counter | |
| 15. |
This type of register accepts inputs data serially |
| A. | PIPO |
| B. | SIPO |
| C. | PISO |
| D. | SISO |
| Answer» E. | |
| 16. |
In asynchronous flip-flop, ______________ and clear pin shows negation. |
| A. | Bubble at the rest |
| B. | Active low preset |
| C. | Clear input |
| D. | Active high preset |
| Answer» B. Active low preset | |
| 17. |
The number of states through which the counter goes is also known as ____________. |
| A. | Counter |
| B. | Latch circuit |
| C. | Multiplexer |
| D. | MOD number |
| Answer» E. | |
| 18. |
Which table indicates the input conditions of the flip-flops necessary to cause all possible next state transitions of a flip-flop? |
| A. | T characteristic |
| B. | Truth |
| C. | Flip- flop excitation |
| D. | Excitation |
| Answer» D. Excitation | |
| 19. |
It is used to subtract two inputs having more than one bit |
| A. | Full Subtractor Circuit |
| B. | Half Subtractor |
| C. | Multiplexer |
| D. | Counter |
| Answer» B. Half Subtractor | |
| 20. |
The speed of conversion is maximum in |
| A. | Successive-approximation A/D converter |
| B. | Parallel-comparative A/D converter |
| C. | Counter ramp A/D converter |
| D. | Dual-slope A/D converter |
| Answer» C. Counter ramp A/D converter | |
| 21. |
It is the converse of decoding and contains 2^n (or fewer) input lines and n output lines |
| A. | Subtractor |
| B. | Decoder |
| C. | Multiplexer |
| D. | Encoder |
| Answer» E. | |
| 22. |
A PLA consists of two-level____________ circuits on a single chip. |
| A. | AND-OR |
| B. | NOR-NAND |
| C. | XOR-AND |
| D. | OR-NAND |
| Answer» B. NOR-NAND | |
| 23. |
It directs data from input to a selected output line |
| A. | Demultiplexer |
| B. | Multiplexer |
| C. | Coder |
| D. | Both a and b |
| Answer» B. Multiplexer | |
| 24. |
The logic 0 level of a CMOS logic device is approximately |
| A. | 1.2 volts |
| B. | 0.4 volts |
| C. | 5 volts |
| D. | 0 volts |
| Answer» E. | |
| 25. |
The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________________ inputs. |
| A. | Sequential |
| B. | Asynchronous |
| C. | Synchronous |
| D. | Both a and b |
| Answer» D. Both a and b | |
| 26. |
It contains an equal resistor or current source segment for each possible value of DAC output. |
| A. | Hybrid DAC |
| B. | Binary weighted DAC |
| C. | Segmented DAC |
| D. | R-2R Ladder DAC |
| Answer» D. R-2R Ladder DAC | |
| 27. |
In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter’s output. This is done to |
| A. | Improve the speed of operation. |
| B. | Reduce the maximum quantization error. |
| C. | Increase the number of bits at the output. |
| D. | Increase the range of input voltage that can be converted. |
| Answer» C. Increase the number of bits at the output. | |
| 28. |
A NOR gate has two or more input signals. All input must be _____ to get a high output. |
| A. | low |
| B. | high |
| C. | some low some high |
| D. | 1's |
| Answer» B. high | |
| 29. |
The __________latch is an asynchronous flip-flop which can be constructed from two NAND gates connected back to back. |
| A. | R-S |
| B. | JK |
| C. | SR |
| D. | None of the above |
| Answer» B. JK | |
| 30. |
This type of register accepts inputs data simultaneously and output is also coming out parallel |
| A. | PIPO |
| B. | SIPO |
| C. | PISO |
| D. | SISO |
| Answer» B. SIPO | |
| 31. |
A demultiplexer can be used as |
| A. | Encoder |
| B. | Decoder |
| C. | Multiplexer |
| D. | None of the above |
| Answer» C. Multiplexer | |
| 32. |
The steps required for the analysis of combinational circuits are |
| A. | Label the inputs and outputs |
| B. | Obtain the functions of intermediate points and the outputs |
| C. | Draw the truth table |
| D. | All of the above |
| Answer» E. | |
| 33. |
There are ___________ basic types of shift registers. |
| A. | Six |
| B. | Four |
| C. | One |
| D. | Many |
| Answer» C. One | |
| 34. |
When the set of input data to an even parity generator is 0111, the output will be |
| A. | 1 |
| B. | 0 |
| C. | Unpredictable |
| D. | Depends on the previous input |
| Answer» C. Unpredictable | |
| 35. |
Which of the following is the advantage of PLD over ICs? |
| A. | Short design cycle |
| B. | Low development cost |
| C. | Flexible to experiment |
| D. | All of the above |
| Answer» E. | |
| 36. |
Read Only Memory (ROM), as the name suggests, is meant only for __________information from it. |
| A. | Reading/writing |
| B. | Writing |
| C. | Reading |
| D. | All the above |
| Answer» D. All the above | |
| 37. |
The number of resistors required for an N-bit DAC is 2N in the case of _____________. |
| A. | Weighted resistor type DAC |
| B. | Binary weighted DAC |
| C. | Segmented DAC |
| D. | R-2R ladder DAC |
| Answer» E. | |
| 38. |
The device which changes from serial data to parallel data is |
| A. | COUNTER |
| B. | MULTIPLEXER |
| C. | DEMULTIPLEXER |
| D. | FLIP-FLOP |
| Answer» D. FLIP-FLOP | |
| 39. |
In this type of register, data can be shifted in either right or left direction by using control signal. |
| A. | PIPO |
| B. | SISO |
| C. | Bi-directional Shift Register |
| D. | None of the above |
| Answer» D. None of the above | |
| 40. |
In which of the following types of counters, the flip-flops do not change states at exactly the same time? |
| A. | Decade counter |
| B. | Asynchronous counter with MOD < 2^n |
| C. | Asynchronous ripple counter |
| D. | Cascading asynchronous counter |
| Answer» D. Cascading asynchronous counter | |
| 41. |
It is a very useful combinational circuit used in communication systems. |
| A. | Parity bit Checker |
| B. | Parity bit Generator |
| C. | Parity bit |
| D. | Both a and b |
| Answer» E. | |
| 42. |
In this type of counter, the output of the last stage is connected to the D input of the first stage. |
| A. | Ring Counter |
| B. | Johnson Counter |
| C. | Straight Counter |
| D. | All of the above |
| Answer» B. Johnson Counter | |
| 43. |
To start the conversion in successive approximation DAC the programmer sets the MSB to ___________ and all other bits to __________. |
| A. | 0,0 |
| B. | 0,1 |
| C. | 1,0 |
| D. | 1,1 |
| Answer» D. 1,1 | |
| 44. |
It is a sequential circuit that cycles through a sequence of states. |
| A. | Multiplexer |
| B. | Demultiplexer |
| C. | Counter |
| D. | Ripple |
| Answer» D. Ripple | |
| 45. |
A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be |
| A. | 15 ns |
| B. | 30 ns |
| C. | 45 ns |
| D. | 60 ns |
| Answer» B. 30 ns | |
| 46. |
Which TTL logic gate is used for wired ANDing |
| A. | Open collector output |
| B. | Totem Pole |
| C. | Tri state output |
| D. | ECL gates |
| Answer» B. Totem Pole | |
| 47. |
ABCD - seven segment decoder / driver in connected to an LED display. Which segments are illuminated for the input code DCBA = 0001. |
| A. | b, c |
| B. | c, b |
| C. | a, b, c |
| D. | a, b, c, d |
| Answer» B. c, b | |
| 48. |
Decoders often come with an enable signal, so that the device is only activated when the enable E equals to ___________. |
| A. | 2 |
| B. | 1 |
| C. | 3 |
| D. | Either a or b |
| Answer» C. 3 | |
| 49. |
The number of control lines for 32 to 1 multiplexer is |
| A. | 4 |
| B. | 5 |
| C. | 16 |
| D. | 6 |
| Answer» C. 16 | |
| 50. |
In the AND gate, the output is ‘High’ or gate is ‘On’ only if both the inputs are ______________. |
| A. | Fluctuating |
| B. | Low |
| C. | Medium |
| D. | High |
| Answer» E. | |