MCQOPTIONS
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MCQOPTIONS
This section includes 950 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Science Engineering (CSE) knowledge and support exam preparation. Choose a topic below to get started.
| 751. |
IDE disk is connected to the PCI BUS using               interface. |
| A. | isa |
| B. | iso |
| C. | ansi |
| D. | ieee |
| Answer» B. iso | |
| 752. |
The system developed by IBM with ISA architecture is |
| A. | sparc |
| B. | sun-sparc |
| C. | pc-at |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 753. |
SCSI stands for |
| A. | signal computer system interface |
| B. | small computer system interface |
| C. | small coding system interface |
| D. | signal coding system interface |
| Answer» C. small coding system interface | |
| 754. |
What is the full form of ANSI? |
| A. | american national standards institute |
| B. | architectural national standards institute |
| C. | asian national standards institute |
| D. | none of the mentioned |
| Answer» B. architectural national standards institute | |
| 755. |
What is the full form of ISA? |
| A. | international american standard |
| B. | industry standard architecture |
| C. | international standard architecture |
| D. | none of the mentioned |
| Answer» C. international standard architecture | |
| 756. |
                  is an extension of the processor BUS. |
| A. | scsi bus |
| B. | usb |
| C. | pci bus |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 757. |
              is used as an intermediate to extend the processor BUS. |
| A. | bridge |
| B. | router |
| C. | connector |
| D. | gateway |
| Answer» B. router | |
| 758. |
Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing? |
| A. | mouse |
| B. | magnetic disk |
| C. | visual display terminal |
| D. | card punch |
| Answer» B. magnetic disk | |
| 759. |
User programmable terminals that combine VDT hardware with built-in microprocessor is |
| A. | kips |
| B. | pc |
| C. | mainframe |
| D. | intelligent terminals |
| Answer» E. | |
| 760. |
The status flags required for data transfer is present in |
| A. | device |
| B. | device driver |
| C. | interface circuit |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 761. |
The Interface circuits generate the appropriate timing signals required by the BUS control scheme. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 762. |
The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 763. |
What is the interface circuit? |
| A. | helps in installing of the software driver for the device |
| B. | houses the buffer that helps in data transfer |
| C. | helps in the decoding of the address on the address bus |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 764. |
The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is |
| A. | bus side |
| B. | port side |
| C. | hardwell side |
| D. | software side |
| Answer» C. hardwell side | |
| 765. |
              serves as an intermediary between the device and the BUSes. |
| A. | interface circuits |
| B. | device drivers |
| C. | buffers |
| D. | none of the mentioned |
| Answer» B. device drivers | |
| 766. |
The asynchronous BUS mode of transmission allows for a faster mode of data transfer. |
| A. | true |
| B. | false |
| Answer» C. | |
| 767. |
Asynchronous mode of transmission is suitable for systems with multiple peripheral devices. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 768. |
The transmission on the asynchronous BUS is also called |
| A. | switch mode transmission |
| B. | variable transfer |
| C. | bulk transfer |
| D. | hand-shake transmission |
| Answer» E. | |
| 769. |
The BUS that allows I/O, memory and Processor to coexist is |
| A. | attributed bus |
| B. | processor bus |
| C. | backplane bus |
| D. | external bus |
| Answer» D. external bus | |
| 770. |
MRDC stands for |
| A. | memory read enable |
| B. | memory ready command |
| C. | memory re-direct command |
| D. | none of the mentioned |
| Answer» C. memory re-direct command | |
| 771. |
The meter in and out lines are used for |
| A. | monitoring the usage of devices |
| B. | monitoring the amount of data transferred |
| C. | measure the cpu usage |
| D. | none of the mentioned |
| Answer» B. monitoring the amount of data transferred | |
| 772. |
In IBM’s S360/370 systems            lines are used to select the I/O devices. |
| A. | scan in and out |
| B. | connect |
| C. | search |
| D. | peripheral |
| Answer» B. connect | |
| 773. |
The MSYN signal is initiated |
| A. | soon after the address and commands are loaded |
| B. | soon after the decoding of the address |
| C. | after the slave gets the commands |
| D. | none of the mentioned |
| Answer» C. after the slave gets the commands | |
| 774. |
Which is fed into the BUS first by the initiator? |
| A. | data |
| B. | address |
| C. | commands or controls |
| D. | address, commands or controls |
| Answer» E. | |
| 775. |
The Master strobes the slave at the end of each clock cycle in Synchronous BUS. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 776. |
The time for which the data is to be on the BUS is affected by |
| A. | propagation delay of the circuit |
| B. | setup time of the device |
| C. | memory access time |
| D. | propagation delay of the circuit & setup time of the device |
| Answer» E. | |
| 777. |
The devices with variable speeds are usually connected using asynchronous BUS. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 778. |
The delays caused in the switching of the timing signals is due to |
| A. | memory access time |
| B. | wmfc |
| C. | propagation delay |
| D. | processor delay |
| Answer» D. processor delay | |
| 779. |
The device which interacts with the initiator is |
| A. | slave |
| B. | master |
| C. | responder |
| D. | friend |
| Answer» B. master | |
| 780. |
The device which starts data transfer is called |
| A. | master |
| B. | transactor |
| C. | distributor |
| D. | initiator |
| Answer» E. | |
| 781. |
In synchronous BUS, the devices get the timing signals from |
| A. | timing generator in the device |
| B. | a common clock line |
| C. | timing signals are not used at all |
| D. | none of the mentioned |
| Answer» C. timing signals are not used at all | |
| 782. |
How is a device selected in Distributed arbitration? |
| A. | to connect the various devices to the cpu |
| B. | to provide a path for communication between the processor and other devices |
| C. | to facilitate data transfer between various devices |
| D. | all of the mentioned |
| Answer» B. to provide a path for communication between the processor and other devices | |
| 783. |
In Distributed arbitration, the device requesting the BUS |
| A. | asserts the start arbitration signal |
| B. | sends an interrupt signal |
| C. | sends an acknowledge signal |
| D. | none of the mentioned |
| Answer» B. sends an interrupt signal | |
| 784. |
If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration. |
| A. | device a |
| B. | device b |
| C. | insufficient information |
| D. | none of the mentioned |
| Answer» C. insufficient information | |
| 785. |
The BUS busy line is used |
| A. | to indicate the processor is busy |
| B. | to indicate that the bus master is busy |
| C. | to indicate the bus is already allocated |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 786. |
After the device completes its operation            assumes the control of the BUS. |
| A. | another device |
| B. | processor |
| C. | controller |
| D. | none of the mentioned |
| Answer» C. controller | |
| 787. |
When the processor receives the request from a device, it responds by sending |
| A. | open-drain circuit |
| B. | open-collector circuit |
| C. | ex-or circuit |
| D. | nor circuit |
| Answer» C. ex-or circuit | |
| 788. |
Once the BUS is granted to a device |
| A. | it activates the bus busy line |
| B. | performs the required operation |
| C. | raises an interrupt |
| D. | all of the mentioned |
| Answer» B. performs the required operation | |
| 789. |
The circuit used for the request line is a |
| A. | open-collector |
| B. | ex-or circuit |
| C. | open-drain |
| D. | nand circuit |
| Answer» D. nand circuit | |
| 790. |
The device which is allowed to initiate data transfers on the BUS at any time is called |
| A. | bus master |
| B. | processor |
| C. | bus arbitrator |
| D. | controller |
| Answer» B. processor | |
| 791. |
              BUS arbitration approach uses the involvement of the processor. |
| A. | centralised arbitration |
| B. | distributed arbitration |
| C. | random arbitration |
| D. | all of the mentioned |
| Answer» B. distributed arbitration | |
| 792. |
The Centralised BUS arbitration is |
| A. | acknowledge signal |
| B. | bus grant signal |
| C. | response signal |
| D. | none of the mentioned |
| Answer» C. response signal | |
| 793. |
The DMA transfer is initiated by |
| A. | processor |
| B. | the process being executed |
| C. | i/o devices |
| D. | os |
| Answer» D. os | |
| 794. |
When the process requests for a DMA transfer? |
| A. | then the process is temporarily suspended |
| B. | the process continues execution |
| C. | another process gets executed |
| D. | process is temporarily suspended & another process gets executed |
| Answer» E. | |
| 795. |
To resolve the clash over the access of the system BUS we use |
| A. | multiple bus |
| B. | bus arbitrator |
| C. | priority access |
| D. | none of the mentioned |
| Answer» C. priority access | |
| 796. |
The registers of the controller are |
| A. | 64 bits |
| B. | 24 bits |
| C. | 32 bits |
| D. | 16 bits |
| Answer» D. 16 bits | |
| 797. |
To overcome the conflict over the possession of the BUS we use |
| A. | optimizers |
| B. | bus arbitrators |
| C. | multiple bus structure |
| D. | none of the mentioned |
| Answer» C. multiple bus structure | |
| 798. |
The controller uses            to help with the transfers when handling network interfaces. |
| A. | input buffer storage |
| B. | signal enhancers |
| C. | bridge circuits |
| D. | all of the mentioned |
| Answer» B. signal enhancers | |
| 799. |
The technique where the controller is given complete access to main memory is |
| A. | cycle stealing |
| B. | memory stealing |
| C. | memory con |
| D. | burst mode |
| Answer» E. | |
| 800. |
The technique whereby the DMA controller steals the access cycles of the processor to operate is called |
| A. | fast conning |
| B. | memory con |
| C. | cycle stealing |
| D. | memory stealing |
| Answer» D. memory stealing | |