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This section includes 8 Mcqs, each offering curated multiple-choice questions to sharpen your Vlsi knowledge and support exam preparation. Choose a topic below to get started.
1. |
CMOS domino logic can be expressed diagramatically as |
A. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12a.png"><img alt="CMOS domino logic can be expressed diagrammatically - option a" class="alignnone size-full wp-image-161997" height="264" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12a.png" width="245"/></a> |
B. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12b.png"><img alt="CMOS domino logic can be expressed diagrammatically - option b" class="alignnone size-full wp-image-161998" height="264" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12b.png" width="245"/></a> |
C. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12c.png"><img alt="CMOS domino logic can be expressed diagrammatically - option c" class="alignnone size-full wp-image-161999" height="264" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12c.png" width="245"/></a> |
D. | <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12d.png"><img alt="CMOS domino logic can be expressed diagrammatically - option d" class="alignnone size-full wp-image-162000" height="264" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12d.png" width="245"/></a> |
Answer» B. <a href="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12b.png"><img alt="CMOS domino logic can be expressed diagrammatically - option b" class="alignnone size-full wp-image-161998" height="264" src="https://www.sanfoundry.com/wp-content/uploads/2017/05/vlsi-questions-answers-cmos-logics-q12b.png" width="245"/></a> | |
2. |
In CMOS domino logic _______ is possible. |
A. | inverting structure |
B. | non inverting structure |
C. | inverting and non inverting structure |
D. | very complex design |
Answer» C. inverting and non inverting structure | |
3. |
CMOS domino logic has |
A. | smaller parasitic capacitance |
B. | larger parasitic capacitance |
C. | low operating speed |
D. | very large parasitic capacitance |
Answer» B. larger parasitic capacitance | |
4. |
CMOS domino logic occupies |
A. | smaller area |
B. | larger area |
C. | smaller & larger area |
D. | none of the mentioned |
Answer» B. larger area | |
5. |
CMOS domino logic is same as ______ with inverter at the output line. |
A. | clocked CMOS logic |
B. | dynamic CMOS logic |
C. | gate logic |
D. | switch logic |
Answer» C. gate logic | |
6. |
In CMOS domino logic _____ is used. |
A. | two phase clock |
B. | three phase clock |
C. | one phase clock |
D. | four phase clock |
Answer» D. four phase clock | |
7. |
In dynamic CMOS logic _____ is used. |
A. | two phase clock |
B. | three phase clock |
C. | one phase clock |
D. | four phase clock |
Answer» E. | |
8. |
The power dissipation in Pseudo-nMOS is reduced to about ________ compared to nMOS device. |
A. | 50% |
B. | 30% |
C. | 60% |
D. | 70% |
Answer» D. 70% | |