MCQOPTIONS
Bookmark
Saved Bookmarks
→
Vhdl
→
User Defined Data Types in Vhdl
→
It is possible to use a component twice which was..
1.
It is possible to use a component twice which was declared only once.
A.
True
B.
False
Answer» B. False
Show Answer
Discussion
No Comment Found
Post Comment
Related MCQs
Which of the following must be known to describe a structural model in VHDL?
It is possible to use a component twice which was declared only once.
Which of the following is the correct syntax for component instantiation?
The structural model is similar to___________
What do you mean by component instantiation?
Which of the following is similar to the entity declaration in structural modeling?
What is the basic unit of structural modeling?
Which of the following is not a way of partitioning a design?
Which of the following is defined in structural modeling?
Reply to Comment
×
Name
*
Email
*
Comment
*
Submit Reply