In the circuit shown below, assume that the comparators are ideal and – McqOptions

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1.	In the circuit shown below, assume that the comparators are ideal and all components have zero propagation delay. In one period of the input signal Vin = 6 sin(ωt), the fraction of the time for which the output OUT is in logic state HIGH is
A.	1/12
B.	1/2
C.	2/3
D.	5/6
Answer» E.

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