In following figure find VGG by assuming gate current is negligible fo – McqOptions

MCQOPTIONS

1.	In following figure find VGG by assuming gate current is negligible for the p-channel JFET. (if IDQ = - 6 mA, RS = 0, VDD = -18 V, RD = 2 k&ohm;, IDSS = - 10 mA, IPO = - 3 V)
A.	0.67 V
B.	6.7 V
C.	7 V
D.	0.3 V
Answer» B. 6.7 V

Discussion

No Comment Found

Related MCQs

The parameter β of a BJT change by 300%. If self bias is used in the amplifier using this BJT, the quiescent value of IC and VCE remain almost the same.
Barkhausen criterion is 1 + Avβ = 0.
When negative feedback is used the fractional changes in closed loop gain are desensitized by the factor (1 + Avβ)
A typical value of gm for a FET is about 25 μs.
Assertion (A): The main use of positive feedback is in oscillator circuits.Reason (R): In an oscillator the loop gain Aβ is kept slightly more than unity
Assertion (A): In Darlington pair, the overall β is product of individual βsReason (R): The voltage gain of a base driven amplifier is equal to ac collector voltage divided by ac base voltage
Assertion (A): In class A amplifier the distortion is minimumReason (R): In class A amplifier collector current exists for 360° of input cycle
Assertion (A): A class C amplifier is a timed amplifier which needs a tank circuit as the load in the collector circuit of the transistor for its proper operationReason (R): In class C operation collector current flows for less than 180° of the ac cycle and thus flows in pulses
For oscillations to starts, the loop gain A β of the oscillator must be initially
In a Hartley oscillator the condition for sustained oscillations is . If there exists mutual inductance M between coils L1 and L2, then the above condition will get modified as hfe