For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligibleWhich of the following statements is true?

Q goes to 0 at the CLK transition and goes to 1 when D goes to 1

Q goes to 1 to the CLK transition and stays at 1

Q goes to 0 at the CLK transition and stays at 10

Q goes to 1 at the CLK transition and goes to 0 when D goes to 1

For the circuit shown in the figure, D has a transition from 0 to 1 af

1.	For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligibleWhich of the following statements is true?
A.	Q goes to 1 to the CLK transition and stays at 1
B.	Q goes to 0 at the CLK transition and stays at 10
C.	Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
D.	Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
Answer» D. Q goes to 0 at the CLK transition and goes to 1 when D goes to 1