A CPU has a cache with block size 64 bytes The main memory has K banks each bank bank being c bytes wide consecutive c byte chunks are mapped on consecutiv banks with warp -around All the k banks can be accssed in parallel but tow accesses to the same bank must be serialized A cache block access may involve multiple iterations of parallel Each Iteration requires decoding the bank number s to be accessed in parallel and this takes k /2 ns . the latency of one bank access is 80 ns If c = 2 and k = 24 then latency of retrieving a cache block starting at address zero from main memory is

A CPU has a cache with block size 64 bytes The main memory has K banks

1.	A CPU has a cache with block size 64 bytes The main memory has K banks each bank bank being c bytes wide consecutive c byte chunks are mapped on consecutiv banks with warp -around All the k banks can be accssed in parallel but tow accesses to the same bank must be serialized A cache block access may involve multiple iterations of parallel Each Iteration requires decoding the bank number s to be accessed in parallel and this takes k /2 ns . the latency of one bank access is 80 ns If c = 2 and k = 24 then latency of retrieving a cache block starting at address zero from main memory is
A.	92 ns
B.	104 ns
C.	172 ns
D.	184 ns
Answer» E.

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A CPU has a cache with block size 64 bytes The main memory has K banks each bank bank being c bytes wide consecutive c byte chunks are mapped on consecutiv banks with warp -around All the k banks can be accssed in parallel but tow accesses to the same bank must be serialized A cache block access may involve multiple iterations of parallel Each Iteration requires decoding the bank number s to be accessed in parallel and this takes k /2 ns . the latency of one bank access is 80 ns If c = 2 and k = 24 then latency of retrieving a cache block starting at address zero from main memory is
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