MCQOPTIONS
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MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Preset and clear are asynchronous inputs. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 2. |
Designation used by a flip-flop for the reset is ________ |
| A. | PRE |
| B. | CLR |
| C. | D |
| D. | Q |
| Answer» C. D | |
| 3. |
Asynchronous circuit is also called ________ circuit. |
| A. | Combinational |
| B. | Self-timed |
| C. | Clock circuit |
| D. | Delayed |
| Answer» C. Clock circuit | |
| 4. |
Which of the following is NOT an advantage of asynchronous reset? |
| A. | It is fast |
| B. | It doesn’t require a clock signal to reset the circuit |
| C. | Reset gets the highest priority |
| D. | It may cause metastability |
| Answer» E. | |
| 5. |
Synchronous reset is a fast reset. |
| A. | True |
| B. | False |
| Answer» C. | |
| 6. |
In asynchronous reset, reset is sampled independently of the _______ |
| A. | Enable signal |
| B. | Data input signal |
| C. | Clock signal |
| D. | Output signal |
| Answer» D. Output signal | |
| 7. |
Which of the following is an advantage of a synchronous reset? |
| A. | It is slow |
| B. | It requires a clock signal to reset the circuit |
| C. | It filters the reset signal |
| D. | It needs a stretched reset |
| Answer» D. It needs a stretched reset | |
| 8. |
In synchronous reset, reset is sampled with respect to _______ |
| A. | Enable signal |
| B. | Data input signal |
| C. | Clock signal |
| D. | Output signal |
| Answer» D. Output signal | |
| 9. |
How many types of resets are there in hardware design? |
| A. | One |
| B. | Two |
| C. | Three |
| D. | Four |
| Answer» C. Three | |
| 10. |
Reset is a signal that is used for the initialization of the hardware. |
| A. | True |
| B. | False |
| Answer» B. False | |