MCQOPTIONS
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MCQOPTIONS
This section includes 9 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Which of the following must be known to describe a structural model in VHDL? |
| A. | Number of inputs and outputs |
| B. | Components and their connections |
| C. | Relation between inputs and outputs |
| D. | Value of output for different input combinations |
| Answer» C. Relation between inputs and outputs | |
| 2. |
It is possible to use a component twice which was declared only once. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 3. |
Which of the following is the correct syntax for component instantiation? |
| A. | instantiate : component_name PORT MAP (port_list); |
| B. | label : instantiate COMPONENT PORT MAP (port_list); |
| C. | label : component_name PORT MAP (port_list); |
| D. | label : instantiate component_name PORT MAP (port_list) |
| Answer» D. label : instantiate component_name PORT MAP (port_list) | |
| 4. |
The structural model is similar to___________ |
| A. | Boolean relations of the circuit |
| B. | Schematic block diagram of the circuit |
| C. | Timing relations of the circuit |
| D. | Components of the circuit |
| Answer» C. Timing relations of the circuit | |
| 5. |
What do you mean by component instantiation? |
| A. | To use the component |
| B. | To describe external interface of the component |
| C. | To declare the gate level components |
| D. | To remove any component from the design |
| Answer» B. To describe external interface of the component | |
| 6. |
Which of the following is similar to the entity declaration in structural modeling? |
| A. | Component instantiation |
| B. | Component declaration |
| C. | Port map |
| D. | Generic map |
| Answer» C. Port map | |
| 7. |
What is the basic unit of structural modeling? |
| A. | Process |
| B. | Component declaration |
| C. | Component instantiation |
| D. | Block |
| Answer» D. Block | |
| 8. |
Which of the following is not a way of partitioning a design? |
| A. | Component |
| B. | Block statement |
| C. | Processes |
| D. | Generics |
| Answer» D. Generics | |
| 9. |
Which of the following is defined in structural modeling? |
| A. | The structure of circuit |
| B. | Behavior of circuit on different inputs |
| C. | Data flow from input to output |
| D. | Functional structure |
| Answer» B. Behavior of circuit on different inputs | |