MCQOPTIONS
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MCQOPTIONS
This section includes 15 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
THE_WORD_LINE_IS_DRIVEN_BY_THE______?$ |
| A. | Chip select |
| B. | Address decoder |
| C. | Data line |
| D. | Control line |
| Answer» C. Data line | |
| 2. |
A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____$ |
| A. | 128 X 8 |
| B. | 256 X 4 |
| C. | 512 X 2 |
| D. | 1024 X 1 |
| Answer» E. | |
| 3. |
A_16_X_8_Organisation_of_memory_cells,_can_store_upto______$ |
| A. | 256 bits |
| B. | 1024 bits |
| C. | 512 bits |
| D. | 128 bits |
| Answer» E. | |
| 4. |
In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there. |
| A. | 10 |
| B. | 8 |
| C. | 9 |
| D. | 12 |
| Answer» D. 12 | |
| 5. |
The advantage of CMOS SRAM over the transistor one’s is _________$ |
| A. | Low cost |
| B. | High efficiency |
| C. | High durability |
| D. | Low power consumption |
| Answer» E. | |
| 6. |
The number of external connections required in 16 X 8 memory organisation is _____ |
| A. | 14 |
| B. | 19 |
| C. | 15 |
| D. | 12 |
| Answer» B. 19 | |
| 7. |
Circuits that can hold their state as long as power is applied is _______ |
| A. | Dynamic memory |
| B. | Static memory |
| C. | Register |
| D. | Cache |
| Answer» C. Register | |
| 8. |
The cells in each column are connected to _____? |
| A. | Word line |
| B. | Data line |
| C. | Read line |
| D. | Sense/ Write line |
| Answer» E. | |
| 9. |
The cells in a row are connected to a common line called ______ |
| A. | Work line |
| B. | Word line |
| C. | Length line |
| D. | Principle diagonal |
| Answer» C. Length line | |
| 10. |
VLSI stands for ___________ |
| A. | Very Large Scale Integration |
| B. | Very Large Stand-alone Integration |
| C. | Volatile Layer System Interface |
| D. | None of the mentioned |
| Answer» B. Very Large Stand-alone Integration | |
| 11. |
The logical addresses generated by the cpu are mapped onto physical memory by ____ |
| A. | Relocation register |
| B. | TLB |
| C. | MMU |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 12. |
__________ is the bottleneck, when it comes computer performance. |
| A. | Memory access time |
| B. | Memory cycle time |
| C. | Delay |
| D. | Latency |
| Answer» C. Delay | |
| 13. |
MFC is used to _________ |
| A. | Issue a read signal |
| B. | Signal to the device that the memory read operation is complete |
| C. | Signal the processor the memory operation is complete |
| D. | Assign a device to perform the read operation |
| Answer» D. Assign a device to perform the read operation | |
| 14. |
The minimum time delay between two successive memory read operations is ______ |
| A. | Cycle time |
| B. | Latency |
| C. | Delay |
| D. | None of the mentioned |
| Answer» B. Latency | |
| 15. |
The duration between the read and the mfc signal is ______ |
| A. | Access time |
| B. | Latency |
| C. | Delay |
| D. | Cycle time |
| Answer» B. Latency | |