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This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
1. |
WHEN_TWO_OR_MORE_CLOCK_CYCLES_ARE_USED_TO_COMPLETE_DATA_TRANSFER_IT_IS_CALLED_AS_________?$ |
A. | Single phase clocking |
B. | Multi-phase clocking |
C. | Edge triggered clocking |
D. | None of the mentioned |
Answer» C. Edge triggered clocking | |
2. |
_________signal_is_used_to_show_complete_of_memory_operation.$ |
A. | MFC |
B. | WMFC |
C. | CFC |
D. | None of the mentioned |
Answer» B. WMFC | |
3. |
The input and output of the registers are governed by _________? |
A. | Transistors |
B. | Diodes |
C. | Gates |
D. | Switches |
Answer» E. | |
4. |
The registers, ALU and the interconnecting path together are called as ______ |
A. | Control path |
B. | Flow path |
C. | Data path |
D. | None of the mentioned |
Answer» D. None of the mentioned | |
5. |
Which register is connected to the MUX? |
A. | Y |
B. | Z |
C. | R0 |
D. | Temp |
Answer» B. Z | |
6. |
The transparent register/s is/are __________ |
A. | Y |
B. | Z |
C. | Temp |
D. | All of the mentioned |
Answer» E. | |
7. |
Which register in the processor is single directional? |
A. | MAR |
B. | MDR |
C. | PC |
D. | Temp |
Answer» B. MDR | |
8. |
The PC gets incremented |
A. | After the instruction decoding |
B. | After the IR instruction gets executed |
C. | After the fetch cycle |
D. | None of the mentioned |
Answer» D. None of the mentioned | |
9. |
A common strategy for performance is making various functional units operate parallelly. |
A. | True |
B. | False |
Answer» B. False | |
10. |
The CPU is also called as ________ |
A. | Processor hub |
B. | ISP |
C. | Controller |
D. | All of the mentioned |
Answer» C. Controller | |