MCQOPTIONS
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MCQOPTIONS
This section includes 165 Mcqs, each offering curated multiple-choice questions to sharpen your Electronics knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
When two counters are cascaded, the overall mod number is equal to the __________ of their individual mod numbers. |
| A. | product |
| B. | sum |
| C. | log |
| D. | reciprocal |
| Answer» B. sum | |
| 2. |
Determine the output frequency of the given circuit if the input CLK frequency is 1 MHz. |
| A. | 0.5 MHz |
| B. | 250 kHz |
| C. | 4 MHz |
| D. | 1 KHz |
| Answer» C. 4 MHz | |
| 3. |
A decade counter is also referred to as |
| A. | BCD counter |
| B. | BCD decade counter |
| C. | Modulo - 10 counter |
| D. | Ring counter |
| Answer» D. Ring counter | |
| 4. |
Consider the following statements regarding registers and latches:1. Registers are temporary storage devices, whereas latches are not.2. A latch employs cross-coupled feedback connections.3. A register stores a binary word, whereas a latch does not.The correct statement(s) is/are: |
| A. | 1 only |
| B. | 2 only |
| C. | 1 and 3 |
| D. | 2 and 3 |
| Answer» E. | |
| 5. |
For NOR circuit SR flip flop the not allowed condition is ______. |
| A. | S = 0, R = 0 |
| B. | S = 0, R = 1 |
| C. | S = 1, R = 1 |
| D. | S = 1, R = 0 |
| Answer» D. S = 1, R = 0 | |
| 6. |
Given below are two statements. One is labeled as Assertion (A) and the other is labeled as reason (R):Assertion (A): Clocked R-S flip-flops are considered semi-transparent.Reason (R): The output Q of a clocked R-S flipflop changes state in response to input changes immediately provided ENABLE is high.Choose the correct option |
| A. | Both (A) and (R) are true and (R) is the correct explanation of (A) |
| B. | Both (A) and (R) are true and (R) is not the correct explanation of (A) |
| C. | (A) is true but (R) is false |
| D. | (A) is false but (R) is true |
| Answer» B. Both (A) and (R) are true and (R) is not the correct explanation of (A) | |
| 7. |
A counter is constructed with three D flip-flops. The input-output pairs are named (D0, Q0), (D1, Q1), and (D2, Q2), where the subscript 0 denotes the least significant bit. The output sequence is desired to be the Gray-code sequence 000, 001, 011, 010, 110, 111, 101, and 100, repeating periodically. Note that the bits are listed in the Q2 Q1 Q0 format. The combinational logic expression for D1 is |
| A. | Q2 Q0 + Q1 Q̅0 |
| B. | Q2 Q1 + Q̅2 Q̅1 |
| C. | Q2 Q1 Q0 |
| D. | Q̅2 Q0 + Q1 Q̅0 |
| Answer» E. | |
| 8. |
For the figure shown, each flip flop has a propagation delay of 10 ns. Determine the total propagation delay from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q3. |
| A. | 20 ns |
| B. | 10 ns |
| C. | 30 ns |
| D. | 40 ns |
| Answer» E. | |
| 9. |
Given below is the diagram of a synchronous sequential circuit with one J-K flip-flop and one T flip-flop with their outputs denoted as A and B respectively, with JA = (Aʹ + Bʹ), KA = (A + B), and TB = A.Starting from the initial state (AB = 00), the sequence of states (AB) visited by the circuit is |
| A. | 00 → 01 → 10 → 11 → 00 . |
| B. | 00 → 10 → 01 → 11 → 00 . |
| C. | 00 → 10 → 11 → 01 → 00 |
| D. | 00 → 01 → 11 → 00 .. |
| Answer» C. 00 → 10 → 11 → 01 → 00 | |
| 10. |
A cascaded arrangement of flip-flops, where the output of one flip flop drives the clock input of the following flip flop is known as |
| A. | Synchronous counter |
| B. | ripple counter |
| C. | ring counter |
| D. | up counter |
| Answer» C. ring counter | |
| 11. |
Characteristic equation of T flip flop is: |
| A. | Qn+1 = T’Qn + TQn’ |
| B. | Qn+1 = T’Qn’ + TQn |
| C. | Qn+1 = T Q |
| D. | Qn+1 = T’Qn’ |
| Answer» B. Qn+1 = T’Qn’ + TQn | |
| 12. |
How many Flip flops circuits are needed to divide by 16? |
| A. | Two |
| B. | Four |
| C. | Eight |
| D. | Sixteen |
| Answer» C. Eight | |
| 13. |
A \(10\frac{1}{2}\) digit Counter-timer is set in the ‘frequency mode’ of operation (with Ts = 1 s). For a specific input, the reading obtained is 1000. Without disconnecting this input, the Counter-timer is changed to operate in the ‘Period mode’ and the range selected is microseconds (μs, with fs = 1 MHz). The counter will then display |
| A. | 0 |
| B. | 10 |
| C. | 100 |
| D. | 1000 |
| Answer» E. | |
| 14. |
A self-starting counter is one that can start |
| A. | the sequence from initial count and continues its sequence |
| B. | the sequence from any state among the sequence and continues its normal count sequence |
| C. | from any state but eventually reaches required count sequence |
| D. | None of the above |
| Answer» D. None of the above | |
| 15. |
In the following sequential circuit, the sequence followed by A and B on rising edge of CLK after reset is de-asserted is |
| A. | AB = 10, 11, 00, 10, 11, … |
| B. | AB = 10, 01, 00, 11, 10, … |
| C. | AB = 10, 00, 01, 10, 00, … |
| D. | AB = 11, 01, 00, 10, 11, … |
| Answer» B. AB = 10, 01, 00, 11, 10, … | |
| 16. |
How many FFs are required to build a binary counter circuit to count from 0 to 1023? |
| A. | 1 |
| B. | 6 |
| C. | 10 |
| D. | 24 |
| Answer» D. 24 | |
| 17. |
8-bit registers consist of ___ Flip Flop. |
| A. | 4 |
| B. | 12 |
| C. | 16 |
| D. | 8 |
| Answer» E. | |
| 18. |
In which of the following devices minimum power is dissipated if the devices are used for same object and same operational condition? |
| A. | Bipolar shift registers |
| B. | Dynamic MOS shift registers |
| C. | Static MOS shift registers |
| D. | 2 and 3 both |
| Answer» C. Static MOS shift registers | |
| 19. |
Propagation delay through a master-slave flip flop is given as 1000 ns. The maximum clock frequency that can be used with this flip flop is: |
| A. | 0.1 MHz |
| B. | 100 MHz |
| C. | 10 MHz |
| D. | 1 MHz |
| Answer» E. | |
| 20. |
In _______the flip flop output transition serves as a source for triggering other flip-flops. |
| A. | shift register |
| B. | ripple counter |
| C. | serial adder |
| D. | parallel adder |
| Answer» C. serial adder | |
| 21. |
A divide by 50 counter can be realized by using |
| A. | 5 number of MOD 10 counter |
| B. | 10 number of MOD 10 counter |
| C. | One MOD-5 counter followed by one MOD-10 counter |
| D. | 10 number of MOD 5 counter |
| Answer» D. 10 number of MOD 5 counter | |
| 22. |
An X-Y flip-flop whose characteristic table is given below is to be implemented using a J-K flip-flopXYQn+100101Qn10Q̅n110 This can be done using- |
| A. | J = X, K = Y̅ |
| B. | J = Y, K = X̅ |
| C. | J = X̅, K = Y |
| D. | J = Y̅, K = X |
| Answer» E. | |
| 23. |
A counter is designed using J-K Flip-Flop as shown in fig. its count sequence |
| A. | 001, 001, 010, 011, 100 & repeats |
| B. | 100, 011, 010, 001 & repeats |
| C. | 010, 011, 100, 000, 011 & repeats |
| D. | 101, 110, 111, 000, 001, 011, 100 & repeats |
| Answer» C. 010, 011, 100, 000, 011 & repeats | |
| 24. |
An eight-bit binary ripple UP counter with a modulus of 256 is holding the count 01111111. What will be the count afte 135 clock pulses? |
| A. | 0000 0101 |
| B. | 1111 1001 |
| C. | 0000 0110 |
| D. | 0000 0111 |
| Answer» D. 0000 0111 | |
| 25. |
Consider the circuit below:This circuit is called a |
| A. | Half adder |
| B. | Latch |
| C. | Bit counter |
| D. | PIPO device |
| Answer» C. Bit counter | |
| 26. |
A Flip Flop is a oscillator. |
| A. | four stable |
| B. | bi-stable |
| C. | mono stable |
| D. | three stable. |
| Answer» C. mono stable | |
| 27. |
Master-slave configuration is used in FF to |
| A. | increase its clocking rate |
| B. | reduces power dissipation |
| C. | eliminates race around condition |
| D. | improves its reliability |
| Answer» D. improves its reliability | |
| 28. |
Minimum clock period of the given circuit is _______.tcd = contamination delay,TPD = proportional delay,Tclk_Q = clock to Q delay,Ts = set up time,th = hold time |
| A. | 17 μs |
| B. | 25 μs |
| C. | 9 μs |
| D. | 22 μs |
| Answer» B. 25 μs | |
| 29. |
For a flip-flop formed from two NAND gates as shown in the given figure, the unusable state corresponds to |
| A. | X = 0, Y = 0 |
| B. | X = 0, Y = 1 |
| C. | X = 1, Y = 0 |
| D. | X = 1, Y = 2 |
| Answer» B. X = 0, Y = 1 | |
| 30. |
For designing a sequential circuit, the following steps are used as general methodologyA) State Assignment and transition tableB) State diagramC) State tableD) RealizationE) k-maps and minimal expressionsThe sequence of these steps in order of their execution isChoose the correct answer from the options given below: |
| A. | C, A, B, E, D |
| B. | E, B, A, D, C |
| C. | A, B, E, C, D |
| D. | B, C, A, E, D |
| Answer» E. | |
| 31. |
In a master slave JK flip-flop J = K = 1. The state Qn+1 of the flip-flop after the clock pulse will be |
| A. | 0 |
| B. | 1 |
| C. | Qn |
| D. | Q̅n |
| Answer» E. | |
| 32. |
Analyze the sequential circuit shown above in figure. Assuming that initial state is 00, determine what input sequence would lead to state 11? |
| A. | 1 - 1 |
| B. | 1 - 0 |
| C. | 0 - 0 |
| D. | State 11 is unreachable |
| Answer» E. | |
| 33. |
If the period of a clock waveform is 1 μs, calculated its frequency. |
| A. | 1 KHz |
| B. | 2 KHz |
| C. | 1 MHZ |
| D. | 2 MHZ |
| Answer» D. 2 MHZ | |
| 34. |
A 1 MHz clock is applied to a J-K=1. What is the frequency of the Flip Flop O/P signal? |
| A. | 2 MHz |
| B. | 500 kHz |
| C. | 250 kHz |
| D. | 500 MHz |
| Answer» C. 250 kHz | |
| 35. |
Master-Slave flip-flop is also called |
| A. | Pulse triggered flip-flop |
| B. | Latch |
| C. | Level triggered flip-flop |
| D. | Buffer |
| Answer» B. Latch | |
| 36. |
A new flipflop with inputs X and Y, has the following propertyInputsCurrent stateNext stateXY00Q101QQ̅11Q010QQ Which of the following expresses the next state in terms of X, Y, current state? |
| A. | (X̅ ∧ Q̅) ∨ (Y̅ ∧ Q) |
| B. | (X̅ ∧ Q) ∨ (Y̅ ∧ Q̅) |
| C. | (X ∧ Q̅) ∨ (Y ∧ Q) |
| D. | (X ∧ Q̅) ∨ (Y̅ ∧ Q) |
| Answer» B. (X̅ ∧ Q) ∨ (Y̅ ∧ Q̅) | |
| 37. |
For a 16-bit signed integer, SLC 500 counters can count within the range of: |
| A. | -32,767 to +32,768 |
| B. | -32,765 to +32,764 |
| C. | -32,766 to +32,765 |
| D. | -32,768 to +32,767 |
| Answer» E. | |
| 38. |
A 2-bit synchronous counter using two J-K flip flops is shown. The expressions for the inputs to the J-K flip flops are also shown in the figure. The output sequence of the counter starting from Q1Q2 = 00 is |
| A. | 00 → 11 → 10 → 01 → 00 … |
| B. | 00 → 01 → 10 → 11 → 00 … |
| C. | 00 → 01 → 11 → 10 → 00 … |
| D. | 00 → 10 → 11 → 01 → 00 … |
| Answer» D. 00 → 10 → 11 → 01 → 00 … | |
| 39. |
If the input to a T flip-flop is a 100 MHz signal, the final output of three T flip-flops in a cascade is |
| A. | 1000 MHz |
| B. | 520 MHz |
| C. | 333 MHz |
| D. | 12.5 MHz |
| Answer» E. | |
| 40. |
In a 4-bit modulo counter, the proportional delay of J-K flip-flop is 50 ns. What is the maximum clock frequency that can be used without skipping a count? |
| A. | 2 MHz |
| B. | 5 KHz |
| C. | 4 MHz |
| D. | 5 MHz |
| Answer» E. | |
| 41. |
If a counter having 10 FFS is initially at 0, what count will it hold after 2060 pulses? |
| A. | 000 000 1100 |
| B. | 000 001 1100 |
| C. | 000 001 1000 |
| D. | 000 000 1110 |
| Answer» B. 000 001 1100 | |
| 42. |
In serial shift register number of clocks pulses required to enter a byte is _________ |
| A. | 8 |
| B. | 1 |
| C. | 4 |
| D. | 1 pulse to enter each 1 and no pulse to enter each 0 |
| Answer» B. 1 | |
| 43. |
In the J-K flip-flop, we have J = Q̅ and K = 1 as shown in the figure:Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be |
| A. | 010000 |
| B. | 011001 |
| C. | 010010 |
| D. | 010101 |
| Answer» E. | |
| 44. |
In a NOR Gate based SR latch which condition is not allowed: |
| A. | S = 0 R = 0 |
| B. | S = 1 R = 1 |
| C. | S = 0 R = 1 |
| D. | S = 1 R = 0 |
| Answer» C. S = 0 R = 1 | |
| 45. |
D flip flop can be made from a J-K flip flop by making |
| A. | J = K |
| B. | J = K = 1 |
| C. | J = 0, K = 1 |
| D. | J = K̅ |
| Answer» E. | |
| 46. |
A Shift register in which the output of the last flip-flop is connected to the input of the first flip-flop |
| A. | BCD counter |
| B. | Parallel counter |
| C. | Ripple counter |
| D. | Ring counter |
| Answer» E. | |
| 47. |
A master-slave JK flip-flop consists of |
| A. | a cascade of two SR flip-flops |
| B. | a JK flip-flop connected in series with a D flip-flop |
| C. | two SR flip-flops connected in parallel |
| D. | an SR flip-flop and a T flip-flop |
| Answer» B. a JK flip-flop connected in series with a D flip-flop | |
| 48. |
How many Flip-Flops are required for mod-16 counter? |
| A. | 5 |
| B. | 6 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 49. |
If input to T flip flop is 200 Hz signal, then what will be the output signal frequency if four T flip flops are connected in cascade |
| A. | 200 Hz |
| B. | 50 Hz |
| C. | 800 Hz |
| D. | None of the above |
| Answer» E. | |
| 50. |
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays. |
| A. | 0110110… |
| B. | 0100100… |
| C. | 011101110… |
| D. | 011001100… |
| Answer» B. 0100100… | |