To operate correctly, starting a ring counter requires __________.

clearing one flip-flop and presetting all the others

presetting one flip-flop and clearing all the others

A comparison between ring and johnson counters indicates that:

a ring counter has fewer flip-flops but requires more decoding circuitry

a ring counter has an inverted feedback path

a johnson counter has more flip-flops but less decoding circuitry

a johnson counter has an inverted feedback path

What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

The output word decreases by 2.

The output word decreases by 1.

The output word decreases by 2.

The output word increases by 1.

The output word increases by 2.

Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

input clock pulses are applied only to the first and last stages

input clock pulses are applied only to the last stage

input clock pulses are not used to activate any of the counter stages

input clock pulses are applied simultaneously to each stage

One of the major drawbacks to the use of asynchronous counters is that:

Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.

low-frequency applications are limited because of internal propagation delays

high-frequency applications are limited because of internal propagation delays

Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.

Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.

Synchronous construction reduces the delay time of a counter to the delay of __________.

all flip-flops and gates after a 3 count

165 + Mcqs in Sequential Logic Circuits in Electronics Page 4 McqOptions

151.	A sequence of equally spaced timing pulses may be easily generated by a(n) __________.
A.	ring counter
B.	johnson counter
C.	binary up counter
D.	ripple counter
Answer» B. johnson counter

Discussion

152.	Counters are common components in digital clocks.
A.	1
B.
Answer» B.

Discussion

153.	In an asynchronous counter, each state is clocked by the same pulse.
A.	1
B.
Answer» C.

Discussion

154.	To operate correctly, starting a ring counter requires __________.
A.	clearing one flip-flop and presetting all the others
B.	clearing all the flip-flops
C.	presetting one flip-flop and clearing all the others
D.	presetting all the flip-flops
Answer» D. presetting all the flip-flops

Discussion

155.	A serial-in, serial-out shift register transfers data from one line of a parallel bus to another line one bit at a time.
A.	1
B.
Answer» C.

Discussion

156.	Mod-6 and mod-12 counters are most commonly used in:
A.	frequency counters
B.	multiplexed displays
C.	digital clocks
D.	power consumption meters
Answer» D. power consumption meters

Discussion

157.	A comparison between ring and johnson counters indicates that:
A.	a ring counter has fewer flip-flops but requires more decoding circuitry
B.	a ring counter has an inverted feedback path
C.	a johnson counter has more flip-flops but less decoding circuitry
D.	a johnson counter has an inverted feedback path
Answer» E.

Discussion

158.	What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
A.	The output word decreases by 1.
B.	The output word decreases by 2.
C.	The output word increases by 1.
D.	The output word increases by 2.
Answer» B. The output word decreases by 2.

Discussion

159.	A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
A.	right, one
B.	right, two
C.	left, one
D.	left, three
Answer» B. right, two

Discussion

160.	What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
A.	PIPO
B.	SISO
C.	SIPO
D.	PISO
Answer» C. SIPO

Discussion

161.	What is a shift register that will accept a parallel input and can shift data left or right called?
A.	tri-state
B.	end around
C.	bidirectional universal
D.	conversion
Answer» D. conversion

Discussion

162.	The serial-in, parallel-out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.
A.	1
B.
C.	1
D.
Answer» C. 1

Discussion

163.	Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
A.	input clock pulses are applied only to the first and last stages
B.	input clock pulses are applied only to the last stage
C.	input clock pulses are not used to activate any of the counter stages
D.	input clock pulses are applied simultaneously to each stage
Answer» E.

Discussion

164.	One of the major drawbacks to the use of asynchronous counters is that:
A.	low-frequency applications are limited because of internal propagation delays
B.	high-frequency applications are limited because of internal propagation delays
C.	Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.
D.	Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.
Answer» C. Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications.

Discussion

165.	Synchronous construction reduces the delay time of a counter to the delay of __________.
A.	all flip-flops and gates
B.	a single flip-flop and a gate
C.	all flip-flops and gates after a 3 count
D.	a single gate
Answer» C. all flip-flops and gates after a 3 count

Discussion

Explore topic-wise MCQs in Electronics.

A sequence of equally spaced timing pulses may be easily generated by a(n) __________.

Counters are common components in digital clocks.

In an asynchronous counter, each state is clocked by the same pulse.

To operate correctly, starting a ring counter requires __________.

A serial-in, serial-out shift register transfers data from one line of a parallel bus to another line one bit at a time.

Mod-6 and mod-12 counters are most commonly used in:

A comparison between ring and johnson counters indicates that:

What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the by position(s) for each clock pulse.

What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?

What is a shift register that will accept a parallel input and can shift data left or right called?

The serial-in, parallel-out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

One of the major drawbacks to the use of asynchronous counters is that:

Synchronous construction reduces the delay time of a counter to the delay of __________.

Explore topic-wise MCQs in Electronics.

A sequence of equally spaced timing pulses may be easily generated by a(n) __________.

Counters are common components in digital clocks.

In an asynchronous counter, each state is clocked by the same pulse.

To operate correctly, starting a ring counter requires __________.

A serial-in, serial-out shift register transfers data from one line of a parallel bus to another line one bit at a time.

Mod-6 and mod-12 counters are most commonly used in:

A comparison between ring and johnson counters indicates that:

What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?

What is a shift register that will accept a parallel input and can shift data left or right called?

The serial-in, parallel-out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.

Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:

One of the major drawbacks to the use of asynchronous counters is that:

Synchronous construction reduces the delay time of a counter to the delay of __________.

A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the by position(s) for each clock pulse.