A synchronous counter using two J – K flip flops that goes through the sequence of states: Q1 Q2 = 00 → 10 → 01 → 11 → 00 …. is required. To achieve this, the inputs to the flip flops are

J1 = Q2, K1 = Q2’; J2 = 1, K2 = 1

J1 = Q2, K1 = 0; J2 = Q1’, K2 = Q1

J1 = 1, K1 = 1; J2 = Q1, K2 = Q1

J1 = Q2, K1 = Q2’; J2 = 1, K2 = 1

J1 = Q2’, K1 = Q2; J2 = Q1, K2 = Q1’

Race around condition is associated with ______.

Sequential circuits with level triggered clock

Both Sequential and Combinational circuits

Directions: It consists of two statements, one labelled as the ‘Statement (I)’ and the other as ‘Statement (II). Examine these two statements carefully and select the answer using the codes given below:Statement (I): The collection of all state variables (memory element stored values) at any time, contain all the information about the past, necessary to account for the circuit’s future behaviour.Statement (II): A change in the stored values in memory elements changes the sequential circuit from one state to another.

Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)

Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)

Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)

Statement (I) is true but Statement (II) is false

Statement (I) is false but Statement (II) is true

Single input to multiple outputs

Multiple inputs to a single output

Single input to multiple outputs

Both Multiple inputs to single output & Single input to multiple outputs

Decimal counter using flipflops and feedback, are more popular than a decimal counter of ring type because of

simple decade circuitry required

economy in the number of flipflops

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

0, 1, 3, 5, 7, 9, 11, 13, 15, 0

Match List I with List II and select the correct answer using the code given below the lists: List I List IIA.5551.MicrocontrollerB.741732.RegisterC. 741633.TimerD.80974.Counter

A – 1, B – 2, C – 4, D - 3

A – 3, B – 4, C – 2, D - 1

A – 1, B – 4, C – 2, D - 3

A – 3, B – 2, C – 4, D - 1

A – 1, B – 2, C – 4, D - 3

Match the two lists and choose the correct answer from the code given below:List IList II(a) (i) Positive edge-triggered flip-flop(b) (ii) T-flip-flop(c)(iii) Clocked flip-flop with clear an preset(d)(iv) Negative level triggered flip-flop

(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)

(a)-(iv), (b)-(ii), (c)-(iii), (d)-(i)

(a)-(iv), (b)-(i), (c)-(iii), (d)-(ii)

(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)

(a)-(iv), (b)-(ii), (c)-(i), (d)-(iii)

A master-slave flip flop has the characteristic that

both the master and the slave states are affected at the same time

change in the output is immediately reflected in the output

change in the output occurs when the state of the master is affected

change in the output occurs when the state of the slave is affected

both the master and the slave states are affected at the same time

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input conditions is: P = Q = ‘0’. If the input conditions is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’

either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

165 + Mcqs in Sequential Logic Circuits in Electronics Page 2 McqOptions

51.	A synchronous counter using two J – K flip flops that goes through the sequence of states: Q1 Q2 = 00 → 10 → 01 → 11 → 00 …. is required. To achieve this, the inputs to the flip flops are
A.	J1 = Q2, K1 = 0; J2 = Q1’, K2 = Q1
B.	J1 = 1, K1 = 1; J2 = Q1, K2 = Q1
C.	J1 = Q2, K1 = Q2’; J2 = 1, K2 = 1
D.	J1 = Q2’, K1 = Q2; J2 = Q1, K2 = Q1’
Answer» C. J1 = Q2, K1 = Q2’; J2 = 1, K2 = 1

Discussion

52.	For the circuit shown, the counter state (Q1Q0) follows the sequence
A.	00, 01,10, 11,00 ....
B.	00, 01, 10, 00, 01 ....
C.	00, 01, 11, 00, 01 ....
D.	00,10, 11,00, 10 ....
Answer» C. 00, 01, 11, 00, 01 ....

Discussion

53.	In a positive edge triggered JK flip-flop, a low J and a low K produces :
A.	Low state
B.	Toggle state
C.	high state
D.	No change
Answer» E.

Discussion

54.	Race around condition is associated with ______.
A.	Combinational circuits
B.	Sequential circuits with level triggered clock
C.	Sequential circuits
D.	Both Sequential and Combinational circuits
Answer» C. Sequential circuits

Discussion

55.	Consider the following statements: A multiplexer(a) Selects one of the several inputs and transmits it to a single output(b) Routes the data from a single input to many outputs(c) Converts parallel data into serial data(d) Is a combinational circuitWhich of these statements are correct?
A.	(a), (b) and (d) only
B.	(b), (c) and (d) only
C.	(a), (c) and (d) only
D.	(b) and (c) only
Answer» D. (b) and (c) only

Discussion

56.	For what minimum value of propagation delay in each flip-flop will a 10-bit ripple counter skip a count, when it is clocked at 10 MHz?
A.	5 ns
B.	10 ns
C.	20 ns
D.	40 ns
Answer» C. 20 ns

Discussion

57.	In a D flip flop the out-put state Q is related with D input in what way?
A.	Q is same as D
B.	Q is complement of D
C.	Q is independent of D
D.	Q is dependent of D
Answer» B. Q is complement of D

Discussion

58.	A 6 bit counter is used to count from 0, 1, 2, ......n. The value of n is _____
A.	16
B.	15
C.	32
D.	63
Answer» E.

Discussion

59.	A Mod-6 counter is realized using 3 flip-flops. The counter will skip
A.	4 Counts
B.	3 Counts
C.	2 Counts
D.	Zero Counts
Answer» D. Zero Counts

Discussion

60.	Directions: It consists of two statements, one labelled as the ‘Statement (I)’ and the other as ‘Statement (II). Examine these two statements carefully and select the answer using the codes given below:Statement (I): The collection of all state variables (memory element stored values) at any time, contain all the information about the past, necessary to account for the circuit’s future behaviour.Statement (II): A change in the stored values in memory elements changes the sequential circuit from one state to another.
A.	Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)
B.	Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)
C.	Statement (I) is true but Statement (II) is false
D.	Statement (I) is false but Statement (II) is true
Answer» B. Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation of Statement (I)

Discussion

61.	How many flip-flops are needed to divide the input frequency by 40?
A.	4
B.	5
C.	6
D.	40
Answer» D. 40

Discussion

62.	Multiplexer converts
A.	Multiple inputs to a single output
B.	Single input to multiple outputs
C.	Both Multiple inputs to single output & Single input to multiple outputs
D.	None of these
Answer» B. Single input to multiple outputs

Discussion

63.	Race-around condition occurs in
A.	Multiplexer
B.	ROM
C.	Flip-flops
D.	Voltage regulator
Answer» D. Voltage regulator

Discussion

64.	A circuit has an output that is determined by the present input as well as previous output states, the circuit is known as
A.	Mealy machine
B.	Moore machine
C.	Sequential circuit
D.	None of these
Answer» D. None of these

Discussion

65.	Decimal counter using flipflops and feedback, are more popular than a decimal counter of ring type because of
A.	simple decade circuitry required
B.	economy in the number of flipflops
C.	high speed of operation
D.	its availability in IC form
Answer» C. high speed of operation

Discussion

66.	In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q1Q0 = 00. The state (Q1Q0) after the 333rd clock pulse is
A.	00
B.	01
C.	10
D.	11
Answer» C. 10

Discussion

67.	A 32 bit adder is formed by cascading 4 bit carry look ahead adder. The gate delays (latency) for getting the sum bits is:
A.	16
B.	18
C.	17
D.	19
Answer» C. 17

Discussion

68.	In a 4-stage ripple counter, the propagation delay of a flip-flop is 30 ns. If the pulse width of the strobe is 30 ns, the maximum frequency at which the counter operates reliably is nearly
A.	9.7 MHz
B.	8.4 MHz
C.	6.7 MHz
D.	4.4 MHz
Answer» D. 4.4 MHz

Discussion

69.	Identify the following sequential component.
A.	Master-slave flip flop
B.	Clocked flip flop
C.	J-K flip flop
D.	R-S flip flop
Answer» E.

Discussion

70.	A mod-3 counter is already available. To design a divide by 6 counter, further how many more flip-flops are required?
A.	6
B.	3
C.	2
D.	1
Answer» E.

Discussion

71.	In a J-K flip-flop, if J = K̅, then it acts as a/an:
A.	T flip-flop
B.	D flip-flop
C.	RS flip-flop
D.	Decoder
Answer» C. RS flip-flop

Discussion

72.	Consider the following opinions regarding the advantage and disadvantage of a Mealy model:1. Advantage: Less number of states (hence less hardware)Disadvantage: Input transients are directly conveyed to the output2. Advantage: Output remains stable over the entire clock period.Disadvantage: Input transients persist for a long duration at the output.Which of the above is/are correct?
A.	1 only
B.	2 only
C.	Both 1 and 2
D.	Neither 1 nor 2
Answer» B. 2 only

Discussion

73.	Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
A.	0, 1, 3, 7, 15, 14, 12, 8, 0
B.	0, 1, 3, 5, 7, 9, 11, 13, 15, 0
C.	0, 2, 4, 6, 8, 10, 12, 14, 0
D.	0, 8, 12, 14, 15, 7, 3, 1, 0
Answer» E.

Discussion

74.	Match List I with List II and select the correct answer using the code given below the lists: List I List IIA.5551.MicrocontrollerB.741732.RegisterC. 741633.TimerD.80974.Counter
A.	A – 3, B – 4, C – 2, D - 1
B.	A – 1, B – 4, C – 2, D - 3
C.	A – 3, B – 2, C – 4, D - 1
D.	A – 1, B – 2, C – 4, D - 3
Answer» D. A – 1, B – 2, C – 4, D - 3

Discussion

75.	A three-bit pseudo-random number generator is shown. Initially, the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is:
A.	000
B.	001
C.	010
D.	100
Answer» E.

Discussion

76.	A state diagram of a logic gate which exhibits delay in the output is shown in the figure, where X is the don’t care condition and Q is the output representing the stateThe logic gate represented by the state diagram is
A.	XOR gate
B.	OR gate
C.	AND gate
D.	NAND gate
Answer» E.

Discussion

77.	A 4bit synchronous counter uses flip-flops with a propagation delay time of 25ns each. The maximum possible time required for change of state will be
A.	25 ns
B.	50 ns
C.	75 ns
D.	200 ns
Answer» E.

Discussion

78.	74VHC273 is a
A.	Dual 4 to 1 Mux
B.	Quad 2 to 1 Mux
C.	Quad D type flip-flop
D.	Octal D type flip-flop
Answer» E.

Discussion

79.	A shift register with its complement output (Q’) of the last stage connected to the D-input of the first stage is called:
A.	twisted-ring counter
B.	synchronous counter
C.	asynchronous counter
D.	up-counter
Answer» B. synchronous counter

Discussion

80.	A 4-bit serial-in parallel-out shift register is initially set to 1111. The data 1010 is applied to the input. After 3 clock cycles the output will be:
A.	1100
B.	0101
C.	1011
D.	1010
Answer» C. 1011

Discussion

81.	A 4-bit modulo 16 ripple counter uses JK flip flop. If the propagation delay of each flip flop is 50 ns, The maximum clock frequency that can be used is
A.	20 MHz
B.	10 MHz
C.	5 MHz
D.	4 MHz
Answer» D. 4 MHz

Discussion

82.	Match the two lists and choose the correct answer from the code given below:List IList II(a) (i) Positive edge-triggered flip-flop(b) (ii) T-flip-flop(c)(iii) Clocked flip-flop with clear an preset(d)(iv) Negative level triggered flip-flop
A.	(a)-(iv), (b)-(ii), (c)-(iii), (d)-(i)
B.	(a)-(iv), (b)-(i), (c)-(iii), (d)-(ii)
C.	(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)
D.	(a)-(iv), (b)-(ii), (c)-(i), (d)-(iii)
Answer» C. (a)-(iv), (b)-(iii), (c)-(ii), (d)-(i)

Discussion

83.	Consider the following circuits:1. Full adder2. Half adder3. JK flip-flop4. CounterWhich of the above circuits are classified as sequential logic circuits?
A.	1 and 2
B.	3 and 4
C.	2 and 3
D.	1 and 4
Answer» C. 2 and 3

Discussion

84.	In a JK flip-flop we have J = Q̅ and K = 1 Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be:
A.	010000
B.	011001
C.	010010
D.	010101
Answer» E.

Discussion

85.	In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms w1, w2, w3 and w4
A.	w1
B.	w2
C.	w3
D.	w4
Answer» D. w4

Discussion

86.	In the diagram above, the inverter (NOT gate) and the AND-gates labelled 1 and 2 have delays of 9, 10 and 12 nanosecond(ns), respectively. Wire delays are negligible. For certain values of a and c, together with certain transition of b, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of the glitch is
A.	7 ns
B.	9 ns
C.	11 ns
D.	13 ns
Answer» B. 9 ns

Discussion

87.	MOD12 and MOD6 counters and multipliers are most commonly used as MOD12, MOD6
A.	Frequency counters
B.	Multiplexed displays
C.	Power consumption meters
D.	Digital Clocks
Answer» E.

Discussion

88.	Consider a 3-bit counter, designed using T flip-flop, as shown below:Assuming the initial state of the counter given by PQR as 000, what are the next three states?
A.	001, 010, 000
B.	001, 010, 111
C.	011, 101, 111
D.	011, 101, 000
Answer» E.

Discussion

89.	A 3-bit ripple counter is constructed using three T flip-flops to do the binary counting. The three flip-flops have T-inputs fixed at
A.	0, 0 and 1
B.	1, 0 and 1
C.	0, 1 and 1
D.	1, 1 and 1
Answer» E.

Discussion

90.	A master-slave flip flop has the characteristic that
A.	change in the output is immediately reflected in the output
B.	change in the output occurs when the state of the master is affected
C.	change in the output occurs when the state of the slave is affected
D.	both the master and the slave states are affected at the same time
Answer» D. both the master and the slave states are affected at the same time

Discussion

91.	If a JK FF toggles more than once during one clock cycle, it is called_______
A.	Bouncing
B.	Racing
C.	Pinging
D.	Spiking
Answer» C. Pinging

Discussion

92.	In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input conditions is: P = Q = ‘0’. If the input conditions is changed simultaneously to P = Q = ‘1’, the outputs X and Y are
A.	X = ‘1’, Y = ‘1’
B.	either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’
C.	either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’
D.	X = ‘0’, Y = ‘0’
Answer» C. either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

Discussion

93.	A ripple counter with n flip-flops can function as a
A.	n: 1 counter
B.	n/2: 1 counter
C.	2n: 1 counter
D.	2n: 1 counter
Answer» E.

Discussion

94.	A counter has N flip flop. The total number of states are
A.	N
B.	N2
C.	4N
D.	2n
Answer» E.

Discussion

95.	Consider the following statements:1. Race-around condition occurs in a JK flipflop when the inputs are 1, 12. A flip-flop is used to store one bit of information3. A transparent latch consists of D-type flipflops4. Master-slave configuration is used in a flipflop to store two bits of informationWhich of the above statements are correct?
A.	1, 2 and 3 only
B.	1, 2 and 4 only
C.	3 and 4 only
D.	1, 2, 3 and 4
Answer» B. 1, 2 and 4 only

Discussion

96.	A three stage Johnson counter ring in figure is clocked at a constant frequency of fc from starting state of Q0 Q1 Q2 =101. The frequency of output Q0 Q1 Q2 will be
A.	fc /2
B.	fc/ 6
C.	fc/3
D.	fc/8
Answer» B. fc/ 6

Discussion

97.	In a J-K flip flop, when J = 1 and K = 1 then it will be considered as:
A.	set condition
B.	reset condition
C.	no change
D.	toggle condition
Answer» E.

Discussion

98.	An 8-bit synchronous counter uses flip-flops with a propagation delay of 25 nsec each. The maximum possible time needed for the change of state is:
A.	125 nsec
B.	25 nsec
C.	100 nsec
D.	50 nsec
Answer» C. 100 nsec

Discussion

99.	Assume that a 4-bit serial in/serial out shift register is initially clear. Bits are shifted in from left. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse?
A.	1100
B.	0011
C.	1111
D.	0000
Answer» E.

Discussion

100.	A feature that distinguishes the JK flip flop from the SR flip flop is the
A.	Toggle condition
B.	Preset input
C.	Type of clock
D.	Clear input
Answer» B. Preset input

Discussion

Explore topic-wise MCQs in Electronics.

A synchronous counter using two J – K flip flops that goes through the sequence of states: Q1 Q2 = 00 → 10 → 01 → 11 → 00 …. is required. To achieve this, the inputs to the flip flops are

For the circuit shown, the counter state (Q1Q0) follows the sequence

In a positive edge triggered JK flip-flop, a low J and a low K produces :

Race around condition is associated with ______.

Consider the following statements: A multiplexer(a) Selects one of the several inputs and transmits it to a single output(b) Routes the data from a single input to many outputs(c) Converts parallel data into serial data(d) Is a combinational circuitWhich of these statements are correct?

For what minimum value of propagation delay in each flip-flop will a 10-bit ripple counter skip a count, when it is clocked at 10 MHz?

In a D flip flop the out-put state Q is related with D input in what way?

A 6 bit counter is used to count from 0, 1, 2, ......n. The value of n is _____

A Mod-6 counter is realized using 3 flip-flops. The counter will skip

How many flip-flops are needed to divide the input frequency by 40?

Multiplexer converts

Race-around condition occurs in

A circuit has an output that is determined by the present input as well as previous output states, the circuit is known as

Decimal counter using flipflops and feedback, are more popular than a decimal counter of ring type because of

In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q1Q0 = 00. The state (Q1Q0) after the 333rd clock pulse is

A 32 bit adder is formed by cascading 4 bit carry look ahead adder. The gate delays (latency) for getting the sum bits is:

In a 4-stage ripple counter, the propagation delay of a flip-flop is 30 ns. If the pulse width of the strobe is 30 ns, the maximum frequency at which the counter operates reliably is nearly

Identify the following sequential component.

A mod-3 counter is already available. To design a divide by 6 counter, further how many more flip-flops are required?

In a J-K flip-flop, if J = K̅, then it acts as a/an:

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

Match List I with List II and select the correct answer using the code given below the lists: List I List IIA.5551.MicrocontrollerB.741732.RegisterC. 741633.TimerD.80974.Counter

A three-bit pseudo-random number generator is shown. Initially, the value of output Y = Y2 Y1 Y0 is set to 111. The value of output Y after three clock cycles is:

A state diagram of a logic gate which exhibits delay in the output is shown in the figure, where X is the don’t care condition and Q is the output representing the stateThe logic gate represented by the state diagram is

A 4bit synchronous counter uses flip-flops with a propagation delay time of 25ns each. The maximum possible time required for change of state will be

74VHC273 is a

A shift register with its complement output (Q’) of the last stage connected to the D-input of the first stage is called:

A 4-bit serial-in parallel-out shift register is initially set to 1111. The data 1010 is applied to the input. After 3 clock cycles the output will be:

A 4-bit modulo 16 ripple counter uses JK flip flop. If the propagation delay of each flip flop is 50 ns, The maximum clock frequency that can be used is

Match the two lists and choose the correct answer from the code given below:List IList II(a) (i) Positive edge-triggered flip-flop(b) (ii) T-flip-flop(c)(iii) Clocked flip-flop with clear an preset(d)(iv) Negative level triggered flip-flop

Consider the following circuits:1. Full adder2. Half adder3. JK flip-flop4. CounterWhich of the above circuits are classified as sequential logic circuits?

In a JK flip-flop we have J = Q̅ and K = 1 Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be:

In the circuit shown, choose the correct timing diagram of the output (y) from the given waveforms w1, w2, w3 and w4

MOD12 and MOD6 counters and multipliers are most commonly used as MOD12, MOD6

Consider a 3-bit counter, designed using T flip-flop, as shown below:Assuming the initial state of the counter given by PQR as 000, what are the next three states?

A 3-bit ripple counter is constructed using three T flip-flops to do the binary counting. The three flip-flops have T-inputs fixed at

A master-slave flip flop has the characteristic that

If a JK FF toggles more than once during one clock cycle, it is called_______

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input conditions is: P = Q = ‘0’. If the input conditions is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

A ripple counter with n flip-flops can function as a

A counter has N flip flop. The total number of states are

A three stage Johnson counter ring in figure is clocked at a constant frequency of fc from starting state of Q0 Q1 Q2 =101. The frequency of output Q0 Q1 Q2 will be

In a J-K flip flop, when J = 1 and K = 1 then it will be considered as:

An 8-bit synchronous counter uses flip-flops with a propagation delay of 25 nsec each. The maximum possible time needed for the change of state is:

Assume that a 4-bit serial in/serial out shift register is initially clear. Bits are shifted in from left. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse?

A feature that distinguishes the JK flip flop from the SR flip flop is the