MCQOPTIONS
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MCQOPTIONS
This section includes 9 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
IF_AT_A_TIME_AO_AND_BHE(ACTIVE_LOW)_BOTH_ARE_ZERO_THEN,_THE_CHIP(S)_SELECTED_WILL_BE?$ |
| A. | RAM |
| B. | ROM |
| C. | RAM and ROM |
| D. | ONLY RAM |
| Answer» D. ONLY RAM | |
| 2. |
If (address line) Ao=0 then, the status of address and memory ar? |
| A. | address is even and memory is in ROM |
| B. | address is odd and memory is in ROM |
| C. | address is even and memory is in RAM |
| D. | address is odd and memory is in RAM |
| Answer» D. address is odd and memory is in RAM | |
| 3. |
To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in |
| A. | parallel |
| B. | serial |
| C. | both serial and parallel |
| D. | neither serial nor parallel |
| Answer» B. serial | |
| 4. |
In most of the cases, the method used for decoding that may be used to minimise the required hardware is |
| A. | absolute decoding |
| B. | non-linear decoding |
| C. | linear decoding |
| D. | none |
| Answer» D. none | |
| 5. |
In static memory, the upper 8-bit bank of an available 16-bit memory chip is called |
| A. | upper address memory bank |
| B. | even address memory bank |
| C. | static upper memory |
| D. | odd address memory bank |
| Answer» E. | |
| 6. |
If the microprocessor has 10 address lines, then the number of memory locations it is able to address is |
| A. | 512 |
| B. | 1024 |
| C. | 2048 |
| D. | none |
| Answer» C. 2048 | |
| 7. |
To address a memory location out of N memory locations, the number of address lines required is |
| A. | log N (to the base 2) |
| B. | log N (to the base 10) |
| C. | log N (to the base e) |
| D. | log (2N) (to the base e) |
| Answer» B. log N (to the base 10) | |
| 8. |
If a location is selected, then all the bits in it are accessible using a group of conductors called |
| A. | control bus |
| B. | address bus |
| C. | data bus |
| D. | either address bus or data bus |
| Answer» D. either address bus or data bus | |
| 9. |
The semiconductor memories are organised as __________ dimension(s) of array of memory locations. |
| A. | one dimensional |
| B. | two dimensional |
| C. | three dimensional |
| D. | none |
| Answer» C. three dimensional | |