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This section includes 9 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
1. |
IN_THE_APPLICATION_WHERE_ALL_THE_INTERRUPTING_DEVICES_ARE_OF_EQUAL_PRIORITY,_THE_MODE_USED_IS?$ |
A. | Automatic rotation |
B. | Automatic EOI mode |
C. | Specific rotation |
D. | EOI |
Answer» B. Automatic EOI mode | |
2. |
When non-specific EOI command is issued to 8259A it will automaticall? |
A. | set the ISR |
B. | reset the ISR |
C. | set the INTR |
D. | reset the INTR |
Answer» C. set the INTR | |
3. |
Once the ICW1 is loaded, then the initialization procedure involves |
A. | edge sense circuit is reset |
B. | IMR is cleared |
C. | slave mode address is set to 7 |
D. | all of the mentioned |
Answer» E. | |
4. |
When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a |
A. | input to designate chip is master or slave |
B. | buffer enable |
C. | buffer disable |
D. | none |
Answer» C. buffer disable | |
5. |
In a cascaded mode, the number of vectored interrupts provided by 8259A is |
A. | 4 |
B. | 8 |
C. | 16 |
D. | 64 |
Answer» E. | |
6. |
The interrupt control logic |
A. | manages interrupts |
B. | manages interrupt acknowledge signals |
C. | accepts interrupt acknowledge signal |
D. | all of the mentioned |
Answer» E. | |
7. |
The register that stores the bits required to mask the interrupt inputs is |
A. | In-service register |
B. | Priority resolver |
C. | Interrupt Mask register |
D. | None |
Answer» D. None | |
8. |
The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is |
A. | Interrupt Request Register |
B. | In-Service Register |
C. | Priority resolver |
D. | Interrupt Mask Register |
Answer» B. In-Service Register | |
9. |
The number of hardware interrupts that the processor 8085 consists of is |
A. | 1 |
B. | 3 |
C. | 5 |
D. | 7 |
Answer» D. 7 | |