Explore topic-wise MCQs in Microprocessors.

This section includes 5 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.

1.

The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is

A. 1
B. 2
C. 3
D. 4
Answer» D. 4
Discussion
2.

The LOCK (active low) signal is activated during

A. Ti of first INTA cycle
B. Ts of first INTA cycle
C. Th of second INTA cycle
D. Ts of second INTA cycle
Answer» C. Th of second INTA cycle
Discussion
3.

The signal of 82C288, that enables the cascade address drivers, during INTA cycles is

A. DEN
B. DT/R (active low)
C. MCE
D. MB
Answer» D. MB
Discussion
4.

The slave (which is selected) sends the vector on data bus after the

A. first INTA (active low) pulse from 80286
B. second INTA (active low) pulse from 80286
C. third INTA (active low) pulse from 80286
D. none of the mentioned
Answer» C. third INTA (active low) pulse from 80286
Discussion
5.

Which of the following is the highest priority usage among them?

A. second transfer cycle of a processor extension data transfer
B. third transfer cycle of a processor extension data transfer
C. hold request
D. second byte transfer of 2-byte transfer at an odd address
Answer» E.
Discussion