MCQOPTIONS
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MCQOPTIONS
This section includes 30 Mcqs, each offering curated multiple-choice questions to sharpen your Electronic Engineering (MCQ) questions & answers knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
How is the baud rate determined on the basis of system clock frequency (f) in accordance to mode '0' of serial communication? |
| A. | (oscillator frequency) / 12 |
| B. | [2 |
| C. | [2 |
| D. | 2 |
| Answer» B. [2 | |
| 2. |
What does the instruction XCHD A, @R signify during the data transfer in the program execution? |
| A. | Exchange of register with an accumulator |
| B. | Exchange of direct byte with an accumulator |
| C. | Exchange of indirect RAM with an accumulator |
| D. | Exchange of low order digit indirect RAM with an accumulator |
| Answer» E. | |
| 3. |
How many bytes are supposed to get occupied while subtracting indirect RAM from an accumulator along with borrow under the execution of SUBBA, @R? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 4. |
What does the following pictorial representation of PUSH operation in the stack pointer indicate among the below stated conclusions/inferences?a. Stack Pointer is incremented by 2b. Location 55H in on-chip stack memory gets loaded with 44Hc. Stack Pointer gets initialized by 56Hd. Data Pointer gets loaded with an immediate data 44H which ultimately leads to initialization of stack pointer |
| A. | Only A |
| B. | Only B |
| C. | B & D |
| D. | C & D |
| Answer» E. | |
| 5. |
Match the following a. JC rel -------------------- 1. Jump if direct bit is set & clear bitb. JNC rel ------------------ 2. Jump if direct bit is setc. JB bit, rel --------------- 3. Jump if direct bit is not setd. JBC bit, rel ------------ 4. Jump if carry is sete. JNB bit, rel ------------- 5. Jump if carry is not set |
| A. | A-3, B-2, C-1, D-4, E-5 |
| B. | A-5, B-2, C-4, D-1, E-3 |
| C. | A-5, B-4, C-3, D-2, E-1 |
| D. | A-4, B-5, C-2, D-1, E-3 |
| Answer» E. | |
| 6. |
Consider the below mentioned statements. Which among them is /are approved to be incorrect in case of calling instructions of program branching?a. Absolute Calls instructions specify 11-bit address and calling subroutine within 2K program memory blockb. Long call instructions specify 16-bit address and subroutine anywhere within 64K program memory blockc. Short call instructions specify 16-bit address and subroutine within 4K program memory blockd. All long call and short call instructions specify 11 bit address and the calling subroutine within 16K program memory block |
| A. | Only A |
| B. | B & D |
| C. | A & C |
| D. | C & D |
| Answer» E. | |
| 7. |
Match the following instruction mnemonics with their description.a. CJNE A,direct,rel ------------ 1. Compare immediate to indirect and Jump if not equalb. CJNE A,#data,rel ------------ 2. Compare direct byte to accumulator and Jump if not equalc. CJNE @R, #data,rel ------- 3. Compare immediate to register and Jump if not equald. CJNE R, # data rel -------- 4. Compare immediate to accumulator and Jump if not equal |
| A. | A-1, B-2, C-3, D-4 |
| B. | A-2, B-4, C-1, D-3 |
| C. | A-4, B-3, C-2, D-1 |
| D. | A-2, B-4, C-3, D-1 |
| Answer» C. A-4, B-3, C-2, D-1 | |
| 8. |
Which minimum mode signal is used for demultiplexing the data and address lines with the assistance of an external latch in a microprocessor while accessing memory segment? |
| A. | |
| B. | |
| C. | HOLD |
| D. | ALE |
| Answer» E. | |
| 9. |
Match the following registers with their functions :a. Line Status Register -------------------- 1. Set Up the communication parametersb. Line Control Register ------------------ 2. Sharing of similar addressesc. Transmit & Receive Buffers --------- 3. Status Determination of Tx & Rr |
| A. | A-2, B-1, C-3 |
| B. | A-1, B-2, C-3 |
| C. | A-3, B-1, C-2 |
| D. | A-3, B-2, C-1 |
| Answer» D. A-3, B-2, C-1 | |
| 10. |
Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system? |
| A. | System |
| B. | Behaviour |
| C. | RT |
| D. | Logic |
| Answer» C. RT | |
| 11. |
Which among the below stated lines represent the handshaking variant usually and only controlled by the software in the handshaking process? |
| A. | XON/ XOFF |
| B. | DCD & GND |
| C. | TxD & RxD |
| D. | All of the above |
| Answer» B. DCD & GND | |
| 12. |
What is the purpose of blanking () associated with the 7-segment display operations?a. To turn ON the displayb. To turn OFF the displayc. To pulse modulate the brightness of displayd. To pulse modulate the lightness of display |
| A. | B & C |
| B. | A & D |
| C. | A & B |
| D. | C & D |
| Answer» B. A & D | |
| 13. |
What is the correct chronological order/sequence of steps associated with the latch operations given below?a. Loading the data on output portb. Increment in the digital output functions by using microcontroller pinsc. Application of latch enable signal to desired latch |
| A. | A, B, C |
| B. | A, C, B |
| C. | C, A, B |
| D. | B, A, C |
| Answer» C. C, A, B | |
| 14. |
Which bits assist in determining the IC bit rate during the initialization process of MSSP module in IC mode? |
| A. | SSPADD |
| B. | SSPBUF |
| C. | Both a & b |
| D. | None of the above |
| Answer» B. SSPBUF | |
| 15. |
Which command/s should be essentially written for IC input threshold selection and slew rate control operations? |
| A. | SSPSTAT |
| B. | SSPIF |
| C. | ACKSTAT |
| D. | All of the above |
| Answer» B. SSPIF | |
| 16. |
Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the external interrupt INT? |
| A. | |
| B. | INTEDG |
| C. | PSA |
| D. | RTS |
| Answer» C. PSA | |
| 17. |
Consider the following statements. Which of them is /are incorrect?a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.c. During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.d. goto instruction written in program memory cannot direct theprogram control to ISR. |
| A. | A & B |
| B. | C & D |
| C. | Only A |
| D. | Only C |
| Answer» C. Only A | |
| 18. |
What would be the value of ADC clock source, if both the ADC clock bits are selected to be '1'? |
| A. | F |
| B. | F |
| C. | F |
| D. | F |
| Answer» B. F | |
| 19. |
Which register is suitable for the corresponding count, if the measurement of pulse width is less than 65,535 s along with the frequency of 4 MHz? |
| A. | 4-bit register |
| B. | 8-bit register |
| C. | 16-bit register |
| D. | 32-bit register |
| Answer» D. 32-bit register | |
| 20. |
Which development tool can facilitate the creation and modification of source programs in addition to assembly and higher -level languages? |
| A. | Editor |
| B. | Assembler |
| C. | Debugger |
| D. | High-level language Compiler |
| Answer» B. Assembler | |
| 21. |
Match the HEX codes of LCD with their associated functionsa. 10H ----------------- 1) Shifting of cursor position to rightb. 14H ----------------- 2) Shifting of cursor position to leftc. 18H ----------------- 3) 2 lines & 5 x 7 character fontd. 38H ----------------- 4) Shifting of an entire display to the left |
| A. | A-4, B 1, C-2, D-3 |
| B. | A-3, B 2, C-1, D-4 |
| C. | A-2, B-1, C-4, D-3 |
| D. | A-1, B 2, C-3, D-4 |
| Answer» D. A-1, B 2, C-3, D-4 | |
| 22. |
Which flags are more likely to get affected in status registers byArithmetic and Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution? |
| A. | Carry (C) Flags |
| B. | Zero (Z) Flags |
| C. | Digit Carry (DC) Flags |
| D. | All of the above |
| Answer» E. | |
| 23. |
Which among the below specified major functionalities is/are associated with the programmable timers of PIC?a. Excogitation of Inputs b. Handling of Outputsc. Interpretation of internal timing for program executiond. Provision of OTP for large and small production runs |
| A. | Only C |
| B. | C & D |
| C. | A, B & D |
| D. | A, B & C |
| Answer» E. | |
| 24. |
Which among the below mentioned bits specify the reset status of register in readable format and are usually utilized in sleep mode of PIC? |
| A. | |
| B. | |
| C. | Both a & b |
| D. | None of the above |
| Answer» D. None of the above | |
| 25. |
Which statement is precise in relation to FSR, INDF and indirect addressing mode?a. Address byte must be written in FSR before executing INDF instruction in indirect addressing modeb. Address byte must be written in FSR after executing INDF instruction in indirect addressing modec. Address byte must be written in FSR at the same time during the execution of INDF instruction in indirect addressing moded. Address byte must be always written in FSR as it is independent of any instruction in indirect addressing mode |
| A. | Only A |
| B. | Only B |
| C. | Only A & B |
| D. | A & D |
| Answer» B. Only B | |
| 26. |
Which kind of mode is favourable for pin for indulging in reset operations? |
| A. | Normal mode |
| B. | Sleep mode |
| C. | Power-down mode |
| D. | Any flexible mode |
| Answer» C. Power-down mode | |
| 27. |
What is the purpose of using the start-up timers in an oscillator circuit of PIC? |
| A. | For ensuring the inception and stabilization of an oscillator in a proper manner |
| B. | For detecting the rise in V |
| C. | For enabling or disabling the power-up timers |
| D. | For generating the fixed delay of 72ms on power-up timers |
| Answer» B. For detecting the rise in V | |
| 28. |
Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock sources for operating at the range of 5- 200 kHzin PIC? |
| A. | RC |
| B. | LP (Low-Power Clocking) |
| C. | XT |
| D. | HS (High Speed) |
| Answer» C. XT | |
| 29. |
Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?a. PIC 16C66B. PIC 16C74C. PIC 16C61D. PIC 16C71 |
| A. | A & B |
| B. | C & D |
| C. | A & C |
| D. | B & D |
| Answer» C. A & C | |
| 30. |
What is the correct chronological order of the following steps involved in the LCALL operation?1. Load the value of 16-bit destination address to program counter2. Increment of the program counter by value '3'3. Storage of the higher byte of program counter on the stack4. Increment of the stack pointer by value'1'5. Storage of the lower byte of program counter on the stack6. Increment in the value of stack pointer |
| A. | 5, 3, 1, 6, 2, 4 |
| B. | 1, 3, 2, 5, 4, 6 |
| C. | 2, 4, 5, 6, 3, 1 |
| D. | 5, 3, 6, 2, 4, 1 |
| Answer» D. 5, 3, 6, 2, 4, 1 | |