The copy-back protocol is used ________

To remove the contents of the cache and push it on to the memory

To copy the contents of the memory onto the cache

To update the contents of the memory from the cache

To remove the contents of the cache and push it on to the memory

ANSI stands for _____

American National Standard Interface

American National Standards Institute

American National Standard Interface

American Network Standard Interfacing

American Network Security Interrupt

The benefit of using this approach is ________

It increases the speed of operation

The disadvantage/s of the hardwired approach is ________

It cannot be used for complex instructions

less flexible & cannot be used for complex instructions

55 + Mcqs in Memory System in Computer Organization Page 1 McqOptions

1.	The associative mapping is costlier than direct mapping.
A.	True
B.	False
Answer» B. False

Discussion

2.	The technique of searching for a block by going through all the tags is ______
A.	Linear search
B.	Binary search
C.	Associative search
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

3.	The set-associative map technique is a combination of the direct and associative technique.
A.	True
B.	False
Answer» B. False

Discussion

4.	The copy-back protocol is used ________
A.	To copy the contents of the memory onto the cache
B.	To update the contents of the memory from the cache
C.	To remove the contents of the cache and push it on to the memory
D.	None of the mentioned
Answer» C. To remove the contents of the cache and push it on to the memory

Discussion

5.	The approach where the memory contents are transferred directly to the processor from the memory is called ______
A.	Read-later
B.	Read-through
C.	Early-start
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

6.	The bit used to signify that the cache location is updated is ________
A.	Dirty bit
B.	Update bit
C.	Reference bit
D.	Flag bit
Answer» B. Update bit

Discussion

7.	A RAMBUS which has 18 data lines is called as _______
A.	Extended RAMBUS
B.	Direct RAMBUS
C.	Multiple RAMBUS
D.	Indirect RAMBUS
Answer» C. Multiple RAMBUS

Discussion

8.	The RDRAM chips assembled into larger memory modules called ______
A.	RRIM
B.	DIMM
C.	SIMM
D.	All of the mentioned
Answer» B. DIMM

Discussion

9.	The last on the hierarchy scale of memory devices is ______
A.	Main memory
B.	Secondary memory
C.	TLB
D.	Flash drives
Answer» C. TLB

Discussion

10.	In the memory hierarchy, as the speed of operation increases the memory size also increases.
A.	True
B.	False
Answer» C.

Discussion

11.	EEPROM stands for Electrically Erasable Programmable Read Only Memory.
A.	True
B.	False
Answer» B. False

Discussion

12.	The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______
A.	Memory sticks
B.	Blue-ray devices
C.	Flash memory
D.	CMOS
Answer» D. CMOS

Discussion

13.	In order to read multiple bytes of a row at the same time, we make use of ______
A.	Latch
B.	Shift register
C.	Cache
D.	Memory extension
Answer» B. Shift register

Discussion

14.	The block transfer capability of the DRAM is called ________
A.	Burst mode
B.	Block mode
C.	Fast page mode
D.	Fast frame mode
Answer» D. Fast frame mode

Discussion

15.	The cells in each column are connected to ______
A.	Word line
B.	Data line
C.	Read line
D.	Sense/ Write line
Answer» E.

Discussion

16.	A 16 X 8 Organisation of memory cells, can store upto _____
A.	256 bits
B.	1024 bits
C.	512 bits
D.	128 bits
Answer» E.

Discussion

17.	The word line is driven by the _____
A.	Chip select
B.	Address decoder
C.	Data line
D.	Control line
Answer» C. Data line

Discussion

18.	A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____
A.	128 X 8
B.	256 X 4
C.	512 X 2
D.	1024 X 1
Answer» E.

Discussion

19.	Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is ______
A.	0.0021
B.	0.0038
C.	0.0064
D.	0.0128
Answer» C. 0.0064

Discussion

20.	The RAS and CAS signals are provided by the ______
A.	Mode register
B.	CS
C.	Memory controller
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

21.	The signals are grouped such that mutually exclusive signals are put together.
A.	True
B.	False
Answer» B. False

Discussion

22.	Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is ________
A.	Horizontal organisation
B.	Vertical organisation
C.	Diagonal organisation
D.	None of the mentioned
Answer» C. Diagonal organisation

Discussion

23.	The LRU can be improved by providing a little randomness in the access.
A.	True
B.	False
Answer» B. False

Discussion

24.	The performance of the system is greatly influenced by increasing the level 1 cache.
A.	True
B.	False
Answer» B. False

Discussion

25.	Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster
A.	A
B.	B
C.	Both take the same time
D.	Insufficient information
Answer» B. B

Discussion

26.	The counter that keeps track of how many times a block is most likely used is _______
A.	Count
B.	Reference counter
C.	Use counter
D.	Probable counter
Answer» C. Use counter

Discussion

27.	The associatively mapped virtual memory makes use of _______
A.	TLB
B.	Page table
C.	Frame table
D.	None of the mentioned
Answer» B. Page table

Discussion

28.	If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation)
A.	3
B.	~2
C.	~1
D.	6
Answer» D. 6

Discussion

29.	The physical memory is not as large as the address space spanned by the processor.
A.	True
B.	False
Answer» B. False

Discussion

30.	The method of placing the heads and the discs in an air tight environment is also called as ______
A.	RAID Arrays
B.	ATP tech
C.	Winchester technology
D.	Fleming reduction
Answer» D. Fleming reduction

Discussion

31.	The input and output of the registers are governed by __________
A.	Transistors
B.	Diodes
C.	Gates
D.	Switches
Answer» E.

Discussion

32.	When two or more clock cycles are used to complete data transfer it is called as ________
A.	Single phase clocking
B.	Multi-phase clocking
C.	Edge triggered clocking
D.	None of the mentioned
Answer» C. Edge triggered clocking

Discussion

33.	Is the below code segment correct, for the addition of two numbers?R1in, YinR2out, Select Y, ADD, ZinZout, R3in
A.	True
B.	False
Answer» B. False

Discussion

34.	________ signal is used to show complete of memory operation.
A.	MFC
B.	WMFC
C.	CFC
D.	None of the mentioned
Answer» B. WMFC

Discussion

35.	For a 3 BUS architecture, is the below code correct for adding three numbers?PCout, R = B, Marin, READ, Inc PCWMFCMDRout, R = B, IRinR4outa, R5outb, Select A, ADD, R6in, End
A.	True
B.	False
Answer» B. False

Discussion

36.	The ISA standard Buses are used to connect ___________
A.	RAM and processor
B.	GPU and processor
C.	Harddisk and Processor
D.	CD/DVD drives and Processor
Answer» D. CD/DVD drives and Processor

Discussion

37.	ANSI stands for _____
A.	American National Standards Institute
B.	American National Standard Interface
C.	American Network Standard Interfacing
D.	American Network Security Interrupt
Answer» B. American National Standard Interface

Discussion

38.	The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4 .BR…
A.	True
B.	False
Answer» B. False

Discussion

39.	There exists a separate block consisting of various units to decode an instruction.
A.	True
B.	False
Answer» B. False

Discussion

40.	There exists a separate block to increment the PC in multiple BUS organisation.
A.	True
B.	False
Answer» B. False

Discussion

41.	The benefit of using this approach is ________
A.	It is cost effective
B.	It is highly efficient
C.	It is very reliable
D.	It increases the speed of operation
Answer» E.

Discussion

42.	A sequence of control words corresponding to a control sequence is called _______
A.	Micro routine
B.	Micro function
C.	Micro procedure
D.	None of the mentioned
Answer» B. Micro function

Discussion

43.	The disadvantage/s of the hardwired approach is ________
A.	It is less flexible
B.	It cannot be used for complex instructions
C.	It is costly
D.	less flexible & cannot be used for complex instructions
Answer» E.

Discussion

44.	The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
A.	True
B.	False
Answer» B. False

Discussion

45.	In micro-programmed approach, the signals are generated by ______
A.	Machine instructions
B.	System programs
C.	Utility tools
D.	None of the mentioned
Answer» B. System programs

Discussion

46.	Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.
A.	Starting address generator
B.	Loader
C.	Linker
D.	Clock
Answer» B. Loader

Discussion

47.	Individual control words of the micro routine are called as ______
A.	Micro task
B.	Micro operation
C.	Micro instruction
D.	Micro command
Answer» D. Micro command

Discussion

48.	The special memory used to store the micro routines of a computer is ________
A.	Control table
B.	Control store
C.	Control mart
D.	Control shop
Answer» C. Control mart

Discussion

49.	A word whose individual bits represent a control signal is ______
A.	Command word
B.	Control word
C.	Co-ordination word
D.	Generation word
Answer» C. Co-ordination word

Discussion

50.	The extra time needed to bring the data into memory in case of a miss is called as _____
A.	Delay
B.	Propagation time
C.	Miss penalty
D.	None of the mentioned
Answer» D. None of the mentioned

Discussion

Explore topic-wise MCQs in Computer Organization.

The associative mapping is costlier than direct mapping.

The technique of searching for a block by going through all the tags is ______

The set-associative map technique is a combination of the direct and associative technique.

The copy-back protocol is used ________

The approach where the memory contents are transferred directly to the processor from the memory is called ______

The bit used to signify that the cache location is updated is ________

A RAMBUS which has 18 data lines is called as _______

The RDRAM chips assembled into larger memory modules called ______

The last on the hierarchy scale of memory devices is ______

In the memory hierarchy, as the speed of operation increases the memory size also increases.

EEPROM stands for Electrically Erasable Programmable Read Only Memory.

The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______

In order to read multiple bytes of a row at the same time, we make use of ______

The block transfer capability of the DRAM is called ________

The cells in each column are connected to ______

A 16 X 8 Organisation of memory cells, can store upto _____

The word line is driven by the _____

A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____

Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is ______

The RAS and CAS signals are provided by the ______

The signals are grouped such that mutually exclusive signals are put together.

Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is ________

The LRU can be improved by providing a little randomness in the access.

The performance of the system is greatly influenced by increasing the level 1 cache.

Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster

The counter that keeps track of how many times a block is most likely used is _______

The associatively mapped virtual memory makes use of _______

If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation)

The physical memory is not as large as the address space spanned by the processor.

The method of placing the heads and the discs in an air tight environment is also called as ______

The input and output of the registers are governed by __________

When two or more clock cycles are used to complete data transfer it is called as ________

Is the below code segment correct, for the addition of two numbers?R1in, YinR2out, Select Y, ADD, ZinZout, R3in

________ signal is used to show complete of memory operation.

For a 3 BUS architecture, is the below code correct for adding three numbers?PCout, R = B, Marin, READ, Inc PCWMFCMDRout, R = B, IRinR4outa, R5outb, Select A, ADD, R6in, End

The ISA standard Buses are used to connect ___________

ANSI stands for _____

The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4 .BR…

There exists a separate block consisting of various units to decode an instruction.

There exists a separate block to increment the PC in multiple BUS organisation.

The benefit of using this approach is ________

A sequence of control words corresponding to a control sequence is called _______

The disadvantage/s of the hardwired approach is ________

The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…

In micro-programmed approach, the signals are generated by ______

Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.

Individual control words of the micro routine are called as ______

The special memory used to store the micro routines of a computer is ________

A word whose individual bits represent a control signal is ______

The extra time needed to bring the data into memory in case of a miss is called as _____