MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 6 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Which of the following can be used as a generic in a complex digital design with many inputs and two outputs? |
| A. | Number of outputs |
| B. | Number of inputs |
| C. | Intermediate signals |
| D. | No parameter |
| Answer» C. Intermediate signals | |
| 2. |
Generics in VHDL can be treated as _______ |
| A. | Global variable |
| B. | Local variable |
| C. | Variable |
| D. | Signal |
| Answer» B. Local variable | |
| 3. |
Which function is used to map a generic on design? |
| A. | Port map() |
| B. | Generic() |
| C. | Generic map() |
| D. | Port |
| Answer» D. Port | |
| 4. |
GENERIC (n : INTEGER := 8); In this statement, the mode of generic n is _______ |
| A. | Integer |
| B. | Real |
| C. | Generic |
| D. | No Mode |
| Answer» E. | |
| 5. |
A generic can t be declared in a component declaration. |
| A. | True |
| B. | False |
| Answer» C. | |
| 6. |
In which part of the VHDL code, generics are declared? |
| A. | Package declaration |
| B. | Entity |
| C. | Architecture |
| D. | Configurations |
| Answer» C. Architecture | |