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MCQOPTIONS
This section includes 406 Mcqs, each offering curated multiple-choice questions to sharpen your Graduate Aptitude Test (GATE) knowledge and support exam preparation. Choose a topic below to get started.
| 301. |
Let f(A, B) = A' + B. Simplified expression for function f(f(x + y, y)z) is : |
| A. | x' + z |
| B. | xyz |
| C. | xy' + z |
| D. | None of these |
| Answer» D. None of these | |
| 302. |
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware ? |
| A. | R to X, 1 to Y, T to Z |
| B. | T to X, R to Y, T to Z |
| C. | T to X, R to Y, 0 to Z |
| D. | R to X, 0 to Y, T to Z |
| Answer» B. T to X, R to Y, T to Z | |
| 303. |
Which are the essential prime implicants of the following Boolean function? f(a, b, c) = a'c + ac' + b'c |
| A. | a'c and ac' |
| B. | a'c and b'c |
| C. | a'c only |
| D. | ac' and bc' |
| Answer» B. a'c and b'c | |
| 304. |
Which of the following expressions is equivalent to (A⊕B)⊕C |
| A. | (A+B+C)(A¯+B¯+C¯) |
| B. | (A+B+C)(A¯+B¯+C) |
| C. | ABC+A¯(B⊕C)+B¯(A⊕C) |
| D. | None of the above |
| Answer» D. None of the above | |
| 305. |
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________. |
| A. | 0 |
| B. | 1 |
| C. | 2 |
| D. | 3 |
| Answer» E. | |
| 306. |
The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to |
| A. | AC’+AB+A’C |
| B. | AB’+AC’+A’C |
| C. | A’B+AC’+AB' |
| D. | A’B+AC+AB' |
| Answer» C. A’B+AC’+AB' | |
| 307. |
What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate? |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» C. 5 | |
| 308. |
Given the function F = P′ + QR, where F is a function in three Boolean variables P, Q and R and P′ = !P, consider the following statements. S1: F = Σ (4, 5, 6) S2: F = Σ (0, 1, 2, 3, 7) S3: F = Π (4, 5, 6) S4: F = Π (0, 1, 2, 3, 7) Which of the following is true? |
| A. | S1-False, S2-True, S3-True, S4-False |
| B. | S1-True, S2-False, S3-False, S4-True |
| C. | S1-False, S2-False, S3-True, S4-True |
| D. | S1-True, S2-True, S3-False, S4-False |
| Answer» B. S1-True, S2-False, S3-False, S4-True | |
| 309. |
The number (123456)8 is equivalent to |
| A. | (A72E)16 and (22130232)4 |
| B. | (A72E)16 and (22131122)4 |
| C. | (A73E)16 and (22130232)4 |
| D. | (A62E)16 and (22120232)4 |
| Answer» B. (A72E)16 and (22131122)4 | |
| 310. |
Using a 4-bit 2’s complement arithmetic, which of the following additions will result in an overflow? (i) 1100 + 1100 (ii) 0011 + 0111 (iii) 1111 + 0111 |
| A. | (i) only |
| B. | (ii) only |
| C. | (iii) only |
| D. | (i) and (iii) only |
| Answer» C. (iii) only | |
| 311. |
The total number of prime implicants of the function f(w, x, y, z) = Σ(0, 2, 4, 5, 6, 10) is ________. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 312. |
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using full adders. The total propagation time of this 4-bit binary adder in microseconds is |
| A. | 19.2 microseconds |
| B. | 18.0 microseconds |
| C. | 12.3 microseconds |
| D. | 16.6 microseconds |
| Answer» B. 18.0 microseconds | |
| 313. |
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be: |
| A. | 1, 1, 0 |
| B. | 1, 0, 0 |
| C. | 0, 1, 0 |
| D. | 1, 0, 1 |
| Answer» C. 0, 1, 0 | |
| 314. |
The number of min-terms after minimizing the following Boolean expression is _________.[D′ + AB′ + A′C + AC′D + A′C′D]′ |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 315. |
How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)? |
| A. | 134 |
| B. | 133 |
| C. | 124 |
| D. | 123 |
| Answer» E. | |
| 316. |
Using Booth's Algorithm for multiplication, the multiplier -57 will be recoded as |
| A. | 0 -1 0 0 1 0 0 -1 |
| B. | 1 1 0 0 0 1 1 1 |
| C. | 0 -1 0 0 1 0 0 0 |
| D. | 0 1 0 0 -1 0 0 1 |
| Answer» B. 1 1 0 0 0 1 1 1 | |
| 317. |
The addition of 4-bit, two's complement, binary numbers 1101 and 0100 results in |
| A. | 0001 and an overflow |
| B. | 1001 and no overflow |
| C. | 0001 and no overflow |
| D. | 1001 and an overflow |
| Answer» D. 1001 and an overflow | |
| 318. |
Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation. Then X −Y is _________ |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 0 |
| Answer» B. 2 | |
| 319. |
Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation ? |
| A. | 11, 00 |
| B. | 01, 10 |
| C. | 10, 01 |
| D. | 00, 11 |
| Answer» E. | |
| 320. |
The following bit pattern represents a floating point number in IEEE 754 single precision format 1 10000011 101000000000000000000000 The value of the number in decimal form is |
| A. | -10 |
| B. | -13 |
| C. | -26 |
| D. | None of these |
| Answer» D. None of these | |
| 321. |
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 322. |
Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________ |
| A. | -1 |
| B. | 2 |
| C. | 1 |
| D. | -2 |
| Answer» B. 2 | |
| 323. |
Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is |
| A. | Θ(1) |
| B. | Θ(Log (n)) |
| C. | Θ(√ n) |
| D. | Θ(n) |
| Answer» C. Θ(√ n) | |
| 324. |
In 2' s complement addition, overflow |
| A. | is flagged whenever there is carry from sign bit addition |
| B. | cannot occur when a positive value is added to a negative value |
| C. | is flagged when the carries from sign bit and previous bit match |
| D. | none of the above |
| Answer» C. is flagged when the carries from sign bit and previous bit match | |
| 325. |
In the absolute addressing mode |
| A. | the operand is inside the instruction |
| B. | the address of the operand is inside the instruction |
| C. | the register containing address of the operand is specified inside the instruction |
| D. | the location of the operand is implicit |
| Answer» C. the register containing address of the operand is specified inside the instruction | |
| 326. |
Horizontal microprogramming : |
| A. | does not require use of signal decoders |
| B. | results in larger sized microinstructions than vertical microprogramming |
| C. | uses one bit for each control signal |
| D. | all of the above |
| Answer» E. | |
| 327. |
Consider the following multiplexer where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and f is the output of the multiplexer. EN is the enable input. The function f(x, y, z) implemented by the circuit is : |
| A. | xyz' |
| B. | xy + z |
| C. | x + z |
| D. | None of these |
| Answer» B. xy + z | |
| 328. |
The 2' s complement representation of the decimal value - 15 is |
| A. | 1111 |
| B. | 11111 |
| C. | 111111 |
| D. | 10001 |
| Answer» E. | |
| 329. |
What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program? MVI L, 5DH MVI L, 6BH MOV A, H ADD L |
| A. | AC = 0 and CY = 0 |
| B. | AC = 1 and CY = 1 |
| C. | AC = 1 and CY = 0 |
| D. | AC = 0 and CY = 0 |
| Answer» D. AC = 0 and CY = 0 | |
| 330. |
The performance of a pipelined processor suffers if |
| A. | the pipeline stages have different delays |
| B. | consecutive instructions are dependent on each other |
| C. | the pipeline stages share hardware resources |
| D. | all of the above |
| Answer» E. | |
| 331. |
Consider the circuit given below with initial state Q0 =1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q2 + 2Q1 + Q0.Which one of the following is the correct state sequence of the circuit? |
| A. | 1,3,4,6,7,5,2 |
| B. | 1,2,5,3,7,6,4 |
| C. | 1,2,7,3,5,6,4 |
| D. | 1,6,5,7,2,3,4 |
| Answer» C. 1,2,7,3,5,6,4 | |
| 332. |
In 8085, which of the following modifies the program counter ? |
| A. | Only PCHL instruction |
| B. | Only ADD instructions |
| C. | Only JMP and CALL instructions |
| D. | All instructions |
| Answer» E. | |
| 333. |
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while |
| A. | INTA is active |
| B. | HOLD is active |
| C. | READY is active |
| D. | None of these |
| Answer» B. HOLD is active | |
| 334. |
Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0. Also, consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y? |
| A. | a |
| B. | b |
| C. | c |
| D. | d |
| Answer» D. d | |
| 335. |
Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc). Which of the following is true? |
| A. | f = x1'+ x1x |
| B. | f = x1'x2 + x1x2' |
| C. | f = x1x2 + x1'x2' |
| D. | f = x1 + x2' |
| Answer» D. f = x1 + x2' | |
| 336. |
Which is the most appropriate match for the items in the first column with the items in the second column:X. Indirect Addressing I. Array implementationY. Indexed Addressing II. Writing re-locatable codeZ. Base Register Addressing III. Passing array as parameter |
| A. | (X, III) (Y, I) (Z, II) |
| B. | (X, II) (Y, III) (Z, I) |
| C. | (X, III) (Y, II) (Z, I) |
| D. | (X, I) (Y, III) (Z, II) |
| Answer» B. (X, II) (Y, III) (Z, I) | |
| 337. |
The 2’s complement representation of (−539)10 in hexadecimal is |
| A. | ABE |
| B. | DBC |
| C. | DE5 |
| D. | 9E7 |
| Answer» D. 9E7 | |
| 338. |
A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged |
| A. | a hardware interrupt is needed |
| B. | a software interrupt is needed |
| C. | a privileged instruction (which does not generate an interrupt) is needed |
| D. | a non-privileged instruction (which does not generate an interrupt is needed |
| Answer» C. a privileged instruction (which does not generate an interrupt) is needed | |
| 339. |
Given the following Karnaugh map, which one of the following represents the minimal Sum-Of-Products of the map? |
| A. | xy + y'z |
| B. | wx'y' + xy + xz |
| C. | w'x + y'z + xy |
| D. | xz + y |
| Answer» B. wx'y' + xy + xz | |
| 340. |
Suppose a processor does not have any stack pointer register. Which of the following statements is true? |
| A. | It cannot have subroutine call instruction |
| B. | It can have subroutine call instruction, but no nested subroutine calls |
| C. | Nested subroutine calls are possible, but interrupts are not |
| D. | All sequences of subroutine calls and also interrupts are possible |
| Answer» B. It can have subroutine call instruction, but no nested subroutine calls | |
| 341. |
A processor needs software interrupt to |
| A. | test the interrupt system of the processor |
| B. | implement co-routines |
| C. | obtain system services which need execution of privileged instructions |
| D. | return from subroutine |
| Answer» D. return from subroutine | |
| 342. |
Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.The CPU instruction “push r”, where = A or B, has the specificationM [SP]How many CPU clock cycles are needed to execute the “push r” instruction? |
| A. | 1 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 343. |
The complement of the function F = (A + B’)(C’ + D)(B’ + C) is: |
| A. | A’B + CD’ + BC' |
| B. | AB’ + C’D + B’C |
| C. | AB’ + CD’ + BC |
| D. | AB + BC + CD |
| Answer» B. AB’ + C’D + B’C | |
| 344. |
The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively), |
| A. | 1, 0 |
| B. | 1, 1 |
| C. | 0, 0 |
| D. | 0,1 |
| Answer» B. 1, 1 | |
| 345. |
The 8085 microprocessor responds to the presence of an interrupt |
| A. | As soon as the TRAP pin becomes 'high' |
| B. | By checking the TRAP pin for 'high' status at the end of each instruction fetch |
| C. | By checking the TRAP pin for 'high' status at the end of the execution of each instruction |
| D. | By Checking the TRAP pin for 'high' status at regular intervals |
| Answer» D. By Checking the TRAP pin for 'high' status at regular intervals | |
| 346. |
Consider the values A = 2.0 x 10^30, B =-2.0 x 10^30, C= 1.0, and the sequenceX: = A + B Y: = A + CX: = X + C Y: = Y + B executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be |
| A. | X = 1.0, Y = 1.0 |
| B. | X = 1.0, Y = 0.0 |
| C. | X = 0.0, Y = 1.0 |
| D. | X = 0.0, Y = 0.0 |
| Answer» C. X = 0.0, Y = 1.0 | |
| 347. |
The most appropriate matching for the following pairsX: Indirect addressing 1 : LoopsY: Immediate addressing 2 : PointersZ: Auto decrement addressing 3: Constantsis |
| A. | X-3, Y-2, Z-1 |
| B. | X-I, Y-3, Z-2 |
| C. | X-2, Y-3, Z-1 |
| D. | X-3, Y-l, Z-2 |
| Answer» D. X-3, Y-l, Z-2 | |
| 348. |
The simultaneous equations on the Boolean variables x, y, z and w, have the following solution for x, y, z and w, respectively. |
| A. | 0 1 0 0 |
| B. | 1 1 0 1 |
| C. | 1 0 1 1 |
| D. | 1 0 0 0 |
| Answer» D. 1 0 0 0 | |
| 349. |
To put the 8085 microprocessor in the wait state |
| A. | lower the-HOLD input |
| B. | lower the READY input |
| C. | raise the HOLD input |
| D. | raise the READY input |
| Answer» C. raise the HOLD input | |
| 350. |
Which function does NOT implement the Karnaugh map given below? |
| A. | a |
| B. | b |
| C. | c |
| D. | d |
| Answer» E. | |