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MCQOPTIONS
This section includes 406 Mcqs, each offering curated multiple-choice questions to sharpen your Graduate Aptitude Test (GATE) knowledge and support exam preparation. Choose a topic below to get started.
| 251. |
In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1 bit is assigned for address mode designation. For indirect addressing, the mode bit is |
| A. | 0 |
| B. | 1 |
| C. | Pointer |
| D. | Off - Set |
| Answer» C. Pointer | |
| 252. |
Pipelining improves CPU performance due to? |
| A. | Reduced memory access time |
| B. | Increased clock speed |
| C. | The introduction of parallelism |
| D. | Additional functional units |
| Answer» D. Additional functional units | |
| 253. |
Spatial locality refers to the problem that once a location is referenced |
| A. | It will not be referenced again |
| B. | It will be referenced again |
| C. | A nearby location will be referenced soon |
| D. | None of the above |
| Answer» D. None of the above | |
| 254. |
Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is |
| A. | 1100 0100 |
| B. | 1001 1100 |
| C. | 1010 0101 |
| D. | 1101 0101 |
| Answer» B. 1001 1100 | |
| 255. |
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be |
| A. | 120.4 microseconds |
| B. | 160.5 microseconds |
| C. | 165.5 microseconds |
| D. | 590.0 microseconds |
| Answer» D. 590.0 microseconds | |
| 256. |
Which memory unit has the lowest access time? |
| A. | Cache |
| B. | Registers |
| C. | Magnetic disk |
| D. | Main memory |
| Answer» C. Magnetic disk | |
| 257. |
The Principle of locality justifies the use of |
| A. | Interrupts |
| B. | Threads |
| C. | DMA |
| D. | Cache memory |
| Answer» E. | |
| 258. |
Consider a Boolean function f(w,x,y,z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i₁=⟨w₁,x₁,y₁,z₁⟩ and i₂=⟨w₂,x₂,y₂,z₂⟩ , we would like the function to remain true as the input changes from i₁ to i₂ (i₁ and i₂ differ in exactly one bit position) without becoming false momentarily. Let f(w,x,y,z)=∑(5,7,11,12,13,15) . Which of the following cube covers of f will ensure that the required property is satisfied? |
| A. | w’xz, wxy’, xy’z, wyz |
| B. | wxy, w’xz, wyz |
| C. | wxy’z’, xz, wx’yz |
| D. | wxy’,wyz,wxz,w’xz,xy’z,xyz |
| Answer» E. | |
| 259. |
The system bus consists of |
| A. | Data bus |
| B. | Data bus and address bus |
| C. | Data bus and control bus |
| D. | Data bus, control bus and address bus |
| Answer» E. | |
| 260. |
The sequence of events that happen during a typical fetch operation is ? |
| A. | PC → Mar →Memory → MOR → IR |
| B. | PC → Memory → MDR → IR |
| C. | PC → Memory → IR |
| D. | PC → Mar → Memory → IR |
| Answer» B. PC → Memory → MDR → IR | |
| 261. |
Addressing mode is ………………… |
| A. | Explicitly specified |
| B. | Implied by the instruction |
| C. | Both a and b |
| D. | Neither a nor b |
| Answer» D. Neither a nor b | |
| 262. |
Consider the following register – transfer language: |
| A. | Immediate |
| B. | Indexed |
| C. | Direct |
| D. | Displacement |
| Answer» C. Direct | |
| 263. |
Which addressing mode is suitable for a high-level language statement? |
| A. | Auto increment |
| B. | Indexed |
| C. | Displacement |
| D. | Auto decrement |
| Answer» E. | |
| 264. |
Horizontal micro construction has which of the following attributes? |
| A. | 1 and 2 |
| B. | 2 and 3 |
| C. | 1,2 and 3 |
| D. | None of these |
| Answer» E. | |
| 265. |
Which of the following statement is true regarding ‘HAZARD’? |
| A. | A digital circuit exhibits temporary mal-function. If the i/p’s are having un-even propagation delays. |
| B. | The permanent mal-function is due to the open circuit (or) short circuit of connection lead to the orbit |
| C. | The Hazard can be struck at 0 (or) 1 |
| D. | All |
| Answer» E. | |
| 266. |
The switching expression corresponding to f(A, B,C, D) = Σ (1, 4, 5, 9, 11,12) is |
| A. | BC'D' + A'C'D + AB'D |
| B. | ABC' + ACD + B'C'D |
| C. | ACD' + A'BC' + AC'D' |
| D. | A'BD + ACD' + BCD' |
| Answer» B. ABC' + ACD + B'C'D | |
| 267. |
Which of the following is not a valid class of interrupts? |
| A. | 1 and 3 |
| B. | 1, 2 and 4 |
| C. | 2 and 3 |
| D. | None of the above |
| Answer» E. | |
| 268. |
In four – address instruction format, the number of bytes required to encode an instruction is (assume each address requires 24 bits, and 1 byte is required for operation code) |
| A. | 9 |
| B. | 13 |
| C. | 14 |
| D. | 12 |
| Answer» C. 14 | |
| 269. |
A system that has a lot of crashes, data should be written to the disk using? |
| A. | write – through |
| B. | write – back |
| C. | Both a and b |
| D. | None of the above |
| Answer» C. Both a and b | |
| 270. |
The minimum time delay between the initiations of two independent memory operations is called |
| A. | Access time |
| B. | Cycle time |
| C. | Transfer rate |
| D. | Latency Time |
| Answer» C. Transfer rate | |
| 271. |
A hardware interrupt is |
| A. | Also called an internal interrupt |
| B. | Also called an external interrupt |
| C. | An I/O interrupt |
| D. | A clock interrupt |
| Answer» C. An I/O interrupt | |
| 272. |
How many bits are needed to represent 20 digit decimal number in binary? |
| A. | 62 bits |
| B. | 60 bits |
| C. | 64 bits |
| D. | 66 bits |
| Answer» C. 64 bits | |
| 273. |
The following are some of the sequences of operations in the instruction cycle, which one is the correct sequence? |
| A. | PC → address register |
| B. | Address register →PC Data register → Data from memory Data register → IR PC + 1 → PC |
| C. | Data from memory → Data register PC →Address register Data register → IR PC + 1 → PC |
| D. | None of these |
| Answer» B. Address register →PC Data register → Data from memory Data register → IR PC + 1 → PC | |
| 274. |
Which of the following is the minimization expression for A+A'B+A'B'C+A'B'C'D? |
| A. | ABCD |
| B. | A+B) (C+D) |
| C. | A+B+C+D |
| D. | 1 |
| Answer» D. 1 | |
| 275. |
If doubling the cache line length reduces the miss rate to 3 percent, by how much it reduces the average memory access time? |
| A. | 27.1ns |
| B. | 25.75ns |
| C. | 22.2ns |
| D. | 4.85ns |
| Answer» B. 25.75ns | |
| 276. |
Consider the following situation and fill in the blanks: |
| A. | Data input, Status, data output command |
| B. | Data input, Status control command |
| C. | Control, Status, Data output command |
| D. | Control, Status, data input Command |
| Answer» D. Control, Status, data input Command | |
| 277. |
Consider a binary channel which has 1 – input and 1 – output initially the input is reproduced at output until two consecutive zero’s are received from then onwards output is the bit – wise complement of input complement continuous until two consecutive 1’s are received at input, from then onwards it repeats the behaviour. What will be the minimum number of states in this binary channel. |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 12 |
| Answer» C. 8 | |
| 278. |
A sequence machine is supposed to receive block of 0’s & 1’s the correct operation required 1’s, number of 1’s in 1st block must be odd and number of 0’s in 0’s block must be even. Any violation indicated by machine outputs 1 against 1st bit of opposite block. What will be minimum number of states in the sequence machine? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 279. |
The purpose of latch feedback is? |
| A. | Increase speed |
| B. | Improve performance |
| C. | Uneven propagation |
| D. | All the above |
| Answer» D. All the above | |
| 280. |
In an SR latch made by cross coupling two NAND gates, If both S and R inputs are set to 0, then it will result in |
| A. | q = 0, q’ = 1 |
| B. | q = 1, q’ = 0 |
| C. | q = 1, q’ = 1 |
| D. | Indeterminate states |
| Answer» D. Indeterminate states | |
| 281. |
The minimum number of D flip – flops needed to design a mod – 258 counter is |
| A. | 9 |
| B. | 8 |
| C. | 512 |
| D. | 258 |
| Answer» B. 8 | |
| 282. |
A 10 – bit Asynchronous counter is having initial value 0 1 0 0 0 1 1 1 1 1. How many flip flops are complemented at next clock? |
| A. | 1 |
| B. | 5 |
| C. | 6 |
| D. | 7 |
| Answer» D. 7 | |
| 283. |
A sequential circuit is having one input and 2 states; The clock is initially in state A. It remains in the same state as long as (x=0) (i.e., input =0). If the input is 1, it switches to the state B and remains there as long as input is 0. On receiving 1 it switches back to state A. If it is realized with D – FF. what is the expression for D FF? |
| A. | XQ + XQ’ |
| B. | X’Q’ + XQ |
| C. | X’Q + XQ’ |
| D. | X’Q + X’Q’ |
| Answer» D. X’Q + X’Q’ | |
| 284. |
How many 3 – to – 8 line decoders with an enable input are needed to construct a 6 – to – 64 line decoder without using any other logic gates? |
| A. | 7 |
| B. | 8 |
| C. | 9 |
| D. | 10 |
| Answer» D. 10 | |
| 285. |
Let the 3 variable function f (a, b, c) = Σ (0, 1, 4, 5,7) is realized with 4x1 mux. The select line S₁ & S₀ are connected with A, B. What will be the connections for data inputs? |
| A. | 1, 0, 1, C |
| B. | 1, 0, C, C |
| C. | 1, C, C, C |
| D. | 1, C, C, C |
| Answer» B. 1, 0, C, C | |
| 286. |
Consider a 3-variable function; f(A, B,C) = S (0, 1, 2, 4). It is realized with a 4x1 multiplexer; select lines S₁ S₀ are taken as B, C. Later it was found that select lines have to be interchanged w.r.t the data line in both terminations, Identify the correct statements. |
| A. | All the i/p terminations remains same except I₀ which is to be complemented |
| B. | The terminations have to be reversed |
| C. | The terminations of I₀ and I₂ are to be interchanged |
| D. | No need to change any input terminations |
| Answer» E. | |
| 287. |
The Boolean function x'y' + xy + x'y is equivalent to |
| A. | x' + y' |
| B. | x + y |
| C. | x + y' |
| D. | x' + y |
| Answer» E. | |
| 288. |
The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is |
| A. | BC'D' + A'C'D + AB'D |
| B. | ABC' + ACD + B'C'D |
| C. | ACD' + A'BC' + AC'D' |
| D. | A'BD + ACD' + BCD' |
| Answer» B. ABC' + ACD + B'C'D | |
| 289. |
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in |
| A. | Q = 0, Q' = 1 |
| B. | Q = 1, Q' = 0 |
| C. | Q = 1, Q' = 1 |
| D. | Indeterminate states |
| Answer» E. | |
| 290. |
Let X denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary constants. Consider the following Boolean expression for F over two variables P and Q:F(P, Q) = ( ( 1 X P) X (P X Q) ) X ( (P X Q) X (Q X 0) ) The equivalent expression for F is |
| A. | P + Q |
| B. | (P + Q)' |
| C. | P X Q |
| D. | (P X Q)' |
| Answer» E. | |
| 291. |
Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.f (x, y, a, b){ if (x is 1) y = a; else y = b;}Which one of the following digital logic blocks is the most suitable for implementing this function? |
| A. | Full adder |
| B. | Priority encoder |
| C. | Multiplexer |
| D. | Flip-flop |
| Answer» D. Flip-flop | |
| 292. |
The hexadecimal representation of 6578 is |
| A. | 1AF |
| B. | D78 |
| C. | D71 |
| D. | 32F |
| Answer» B. D78 | |
| 293. |
Consider a Boolean function f (w, x, y, z). suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i1 = (w1, x1, y1, z1) and i2 = (w2, x2, y2, z2) we would like the function to remain true as the input changes from i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f (w, x, y, z) = ∑(5,7,11,12,13,15). Which of the following cube covers of f will ensure that the required property is satisfied? |
| A. | w'xz, wxy', xy'z, xyz,wyz |
| B. | wxy,w'xz,wyz |
| C. | wx(yz)', xz, wx'yz |
| D. | wzy, wyz, wxz, w'xz, xy'z, xyz |
| Answer» B. wxy,w'xz,wyz | |
| 294. |
Let k = 2^n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2^n bit decoder. This circuit is equivalent to a |
| A. | k-bit binary up counter |
| B. | k-bit binary down counter |
| C. | k-bit ring counter |
| D. | k-bit Johnson counter |
| Answer» D. k-bit Johnson counter | |
| 295. |
In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for inputs Ai and Bi are given by:Pi = Ai ⨁ Bi and Gi = AiBi The expressions for the sum bit Si and the carry bit Ci+1 of the look-ahead carry adder are given by:Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry. Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi and Gi are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively: |
| A. | 6, 3 |
| B. | 10, 4 |
| C. | 6, 4 |
| D. | 10, 5 |
| Answer» C. 6, 4 | |
| 296. |
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» C. 4 | |
| 297. |
A 1-input, 2-output synchronous sequential circuit behaves as follows : Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds. zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10. nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01.What is the minimum number of states required in the state transition graph of the above circuit? |
| A. | 5 |
| B. | 6 |
| C. | 7 |
| D. | 8 |
| Answer» B. 6 | |
| 298. |
Consider the operations f(X, Y, Z) = X'YZ + XY' + Y'Z' and g(X′, Y, Z) = X′YZ + X′YZ′ + XY. Which one of the following is correct? |
| A. | Both {f} and {g} are functionally complete |
| B. | Only {f} is functionally complete |
| C. | Only {g} is functionally complete |
| D. | Neither {f} nor {g} is functionally complete |
| Answer» C. Only {g} is functionally complete | |
| 299. |
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is |
| A. | Θ(1) |
| B. | Θ(log n) |
| C. | Θ(n) |
| D. | Θ(n^2) |
| Answer» D. Θ(n^2) | |
| 300. |
A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic. |
| A. | 4 time units |
| B. | 6 time units |
| C. | 10 time units |
| D. | 12 time units |
| Answer» B. 6 time units | |