In 2' s complement addition, overflow – McqOptions

MCQOPTIONS

1.	In 2' s complement addition, overflow
A.	is flagged whenever there is carry from sign bit addition
B.	cannot occur when a positive value is added to a negative value
C.	is flagged when the carries from sign bit and previous bit match
D.	none of the above
Answer» C. is flagged when the carries from sign bit and previous bit match

Discussion

No Comment Found

Related MCQs

Consider the following circuit. Which one of the following is true?
Identify which of the following prime implicant is not valid?
The following truth table represents the Boolean function
What is the minimum number of 2 – input NAND gates are required for realizing the following function?
Consider the following circuit composed of XOR gates and non-inverting buffers.
Consider the following circuit. Except the Buffers, no gate and no connecting lead is having the delay and All inputs and outputs of gates are zero initially. Consider the timining diagram X has made. How many changes does Y undergone?
The following diagram shows, which addressing mode?
Consider on (n+k) bit instruction with a k-bit opcode and single n-bit address. Then this instruction allows…………….. Operations and …………… addressable memory cells.?
Consider the combinational decoder, then find out the expression for the function.
Consider the following state table. What will be the minimum length of input required to table the machine into state ‘C’?