MCQOPTIONS
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MCQOPTIONS
This section includes 5 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The branch target buffer is |
| A. | four-way set-associative memory |
| B. | has branch instruction address |
| C. | has destination address |
| D. | all of the mentioned |
| Answer» E. | |
| 2. |
The memory device that holds branch target addresses for previously executed branches is |
| A. | Tristate buffer |
| B. | RAM |
| C. | ROM |
| D. | Branch target buffer |
| Answer» E. | |
| 3. |
The CPU has to wait until the execution stage to determine whether the condition is met in |
| A. | unconditional branch |
| B. | conditional branch |
| C. | pipelined execution branch |
| D. | none of the mentioned |
| Answer» C. pipelined execution branch | |
| 4. |
The architecture in which the hardware decides which instructions are to be issued concurrently at run time is |
| A. | super pipelined architecture |
| B. | multiple instruction issue |
| C. | very long instruction word architecture |
| D. | superscalar architecture |
| Answer» E. | |
| 5. |
The salient feature of Pentium is |
| A. | superscalar architecture |
| B. | superpipelined architecture |
| C. | superscalar and superpipelined architecture |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |