MCQOPTIONS
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MCQOPTIONS
This section includes 76 Mcqs, each offering curated multiple-choice questions to sharpen your Organization and Architecture Mcqs knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ? |
| A. | OR |
| B. | AND |
| C. | NAND |
| D. | XOR |
| Answer» E. | |
| 2. |
A one-to-four line demultiplexer is to be implemented using a memory. How many bits must each word have ? |
| A. | 1 bit |
| B. | 2 bits |
| C. | 4 bits |
| D. | 8 bits |
| Answer» B. 2 bits | |
| 3. |
What logic function is produced by adding an inverter to the output of an AND gate ? |
| A. | NAND |
| B. | NOR |
| C. | XOR |
| D. | OR |
| Answer» B. NOR | |
| 4. |
Which of the following gates is known as coincidence detector ? |
| A. | AND gate |
| B. | OR gate |
| C. | NOT gate |
| D. | NAND gate |
| Answer» B. OR gate | |
| 5. |
Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ? |
| A. | Function table |
| B. | Truth table |
| C. | Routing table |
| D. | ASCII table |
| Answer» C. Routing table | |
| 6. |
For JK flip flop with J=1, K=0, the output after clock pulse will be |
| A. | 0 |
| B. | 1 |
| C. | High impedance |
| D. | No change |
| Answer» C. High impedance | |
| 7. |
The output of SR flip flop when S=1, R=0 is |
| A. | 1 |
| B. | 0 |
| C. | No change |
| D. | High impedance |
| Answer» B. 0 | |
| 8. |
The number of flip flops contained in IC 7490 is |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 10 |
| Answer» B. 3 | |
| 9. |
How many two-input AND and OR gates are required to realize Y=CD+EF+G |
| A. | 2,2 |
| B. | 2,3 |
| C. | 3,3 |
| D. | None of these |
| Answer» B. 2,3 | |
| 10. |
When an input signal A=11001 is applied to a NOT gate serially, its output signal is |
| A. | 00111 |
| B. | 00110 |
| C. | 10101 |
| D. | 11001 |
| Answer» C. 10101 | |
| 11. |
The result of adding hexadecimal number A6 to 3A is |
| A. | DD |
| B. | E0 |
| C. | F0 |
| D. | EF |
| Answer» C. F0 | |
| 12. |
A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate? |
| A. | OR |
| B. | AND |
| C. | XOR |
| D. | NAND |
| Answer» E. | |
| 13. |
A full adder logic circuit will have |
| A. | Two inputs and one output |
| B. | Three inputs and three outputs |
| C. | Two inputs and two outputs |
| D. | Three inputs and two outputs |
| Answer» E. | |
| 14. |
An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately |
| A. | 1 MHz |
| B. | 500 MHz |
| C. | 2 MHz |
| D. | 4 MHz |
| Answer» B. 500 MHz | |
| 15. |
The output of a JK flipflop with asynchronous preset and clear inputs is 1 . The output can be changed to 0 with one of the following conditions. |
| A. | By applying J = 0, K = 0 and using a clock. |
| B. | By applying J = 1, K = 0 and using the clock. |
| C. | By applying J = 1, K = 1 and using the clock. |
| D. | By applying a synchronous preset input. |
| Answer» D. By applying a synchronous preset input. | |
| 16. |
A weighted resistor digital to analog converter using N bits requires a total of |
| A. | N precision resistors |
| B. | 2N precision resistors |
| C. | N + 1 precision resistors |
| D. | N 1 precision resistors |
| Answer» B. 2N precision resistors | |
| 17. |
How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB ? |
| A. | 1, 1 |
| B. | 4, 2 |
| C. | 3, 2 |
| D. | 2, 3 |
| Answer» B. 4, 2 | |
| 18. |
For JK flipflop J = 0, K=1, the output after clock pulse will be |
| A. | 1 |
| B. | No change |
| C. | 0 |
| D. | High impedance |
| Answer» D. High impedance | |
| 19. |
Which of following are known as universal gates ? |
| A. | NAND & NOR |
| B. | AND & OR |
| C. | XOR & OR |
| D. | None of these |
| Answer» B. AND & OR | |
| 20. |
In the implementation of a Multiplier circuit in the system we make use of _______ . |
| A. | Counter |
| B. | Flip flop |
| C. | Shift register |
| D. | Push down stack |
| Answer» D. Push down stack | |
| 21. |
When 1101 is used to divide 100010010 the remainder is ______ . |
| A. | 101 |
| B. | 11 |
| C. | 0 |
| D. | 1 |
| Answer» E. | |
| 22. |
The correction to be applied in decimal adder to the generated sum is |
| A. | 00101 |
| B. | 00110 |
| C. | 01101 |
| D. | 01010 |
| Answer» C. 01101 | |
| 23. |
The digital logic family which has the lowest propagation delay time is |
| A. | ECL |
| B. | TTL |
| C. | CMOS |
| D. | PMOS |
| Answer» B. TTL | |
| 24. |
How many AND gates are required to realize Y = CD+EF+G |
| A. | 4 |
| B. | 5 |
| C. | 3 |
| D. | 2 |
| Answer» E. | |
| 25. |
How many select lines will a 16 to 1 multiplexer will have |
| A. | 4 |
| B. | 5 |
| C. | 3 |
| D. | 1 |
| Answer» B. 5 | |
| 26. |
CMOS circuits consume power |
| A. | Equal to TTL |
| B. | Less than TTL |
| C. | Twice of TTL |
| D. | Thrice of TTL |
| Answer» C. Twice of TTL | |
| 27. |
The commercially available 8-input multiplexer integrated circuit in the TTL family is |
| A. | 7495 |
| B. | 74153 |
| C. | 74154 |
| D. | 74151 |
| Answer» C. 74154 | |
| 28. |
CMOS circuits are extensively used for ON-chip computers mainly because of their extremely |
| A. | Low power dissipation |
| B. | High noise immunity |
| C. | Large packing density |
| D. | Low cost |
| Answer» D. Low cost | |
| 29. |
Which of the following memories stores the most number of bits |
| A. | a 5M 8 memory |
| B. | A 1M 16 memory |
| C. | a 5M 4 memory |
| D. | A 1M 12 memory |
| Answer» B. A 1M 16 memory | |
| 30. |
Which of the following is the fastest logic? |
| A. | ECL |
| B. | TTL |
| C. | CMOS |
| D. | LSI |
| Answer» B. TTL | |
| 31. |
Shifting a register content to left by one bit position is equivalent to |
| A. | Division by two |
| B. | addition by two |
| C. | Multiplication by two |
| D. | Subtraction by two |
| Answer» D. Subtraction by two | |
| 32. |
A demultiplexer is used to |
| A. | Route the data from single input to one of many outputs |
| B. | Perform serial to parallel conversion |
| C. | Both a & b |
| D. | Select data from several inputs and route it to single output |
| Answer» D. Select data from several inputs and route it to single output | |
| 33. |
How many full adders are required to construct an m-bit parallel adder ? |
| A. | M/2 |
| B. | M-1 |
| C. | M |
| D. | M+1 |
| Answer» C. M | |
| 34. |
The most efficient method followed by computers to multiply two unsigned numbers is _______ . |
| A. | Booth algorithm |
| B. | Bit pair recording of multipliers |
| C. | Restoring algorithm |
| D. | Non restoring algorithm |
| Answer» C. Restoring algorithm | |
| 35. |
For the addition of large integers most of the systems make use of ______ . |
| A. | Fast adders |
| B. | Full adders |
| C. | Carry look-ahead adders |
| D. | None of the above |
| Answer» D. None of the above | |
| 36. |
In a normal n-bit adder , to find out if an overflow as occurred we make use of _____ . |
| A. | And gate |
| B. | Nand gate |
| C. | Nor gate |
| D. | Xor gate |
| Answer» E. | |
| 37. |
Don t care conditions can be used for simplifying Boolean expressions in_______________. |
| A. | Examples |
| B. | Terms |
| C. | K-maps |
| D. | Either a or b |
| Answer» D. Either a or b | |
| 38. |
It should be kept in mind that don t care terms should be used along with the terms that are present in________________. |
| A. | Minterms |
| B. | Maxterm |
| C. | K-Map |
| D. | None of the above |
| Answer» B. Maxterm | |
| 39. |
Using the transformation method, you can realize any POS realization of OR-AND with only |
| A. | XOR |
| B. | NAND |
| C. | AND |
| D. | NOR |
| Answer» E. | |
| 40. |
Logic High at the output is treated as gate ________. |
| A. | On |
| B. | Off |
| C. | 0 |
| D. | None of the above |
| Answer» B. Off | |
| 41. |
In digital electronics, the ON state is often represented by |
| A. | 0 |
| B. | 1 |
| C. | 2 |
| D. | 3 |
| Answer» C. 2 | |
| 42. |
The basic logic gates are NOT, AND and |
| A. | OR |
| B. | XOR |
| C. | XNOR |
| D. | All of the above |
| Answer» E. | |
| 43. |
The output of the NOT gate is always the _______________________ of the input. |
| A. | Same |
| B. | Negation |
| C. | Opposite |
| D. | Both b and c |
| Answer» E. | |
| 44. |
Symbol: F = A.B, where . implies ________________ operation. |
| A. | OR |
| B. | AND |
| C. | XOR |
| D. | NOR |
| Answer» C. XOR | |
| 45. |
A basic OR gate is a two input, _________________ output gate. |
| A. | Two |
| B. | Infinity |
| C. | Single |
| D. | Zero |
| Answer» D. Zero | |
| 46. |
The OR gate output is 0 only when both the inputs are _________________. |
| A. | Minus |
| B. | 2 |
| C. | 1 |
| D. | 0 |
| Answer» E. | |
| 47. |
Symbol: F = A + B, where + implies _____ operation. |
| A. | OR |
| B. | AND |
| C. | NAND |
| D. | XOR |
| Answer» B. AND | |
| 48. |
A gate related to the OR gate is the _____________ or _________________. |
| A. | NOR |
| B. | XOR Gate |
| C. | Exclusive OR Gate |
| D. | Both b and c |
| Answer» E. | |
| 49. |
The XOR output is 1 if the inputs are ______________________ . |
| A. | Different |
| B. | Same |
| C. | Finite |
| D. | Infinite |
| Answer» B. Same | |
| 50. |
Symbol: F = A B, where implies _________ operation. |
| A. | OR |
| B. | XOR |
| C. | NOR |
| D. | NAND |
| Answer» C. NOR | |