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This section includes 2291 Mcqs, each offering curated multiple-choice questions to sharpen your Engineering knowledge and support exam preparation. Choose a topic below to get started.
1451. |
A NAND gate can function as a negative-OR gate. |
A. | True |
B. | False |
Answer» B. False | |
1452. |
An AND gate is a universal gate. |
A. | True |
B. | False |
Answer» C. | |
1453. |
The symbol shown represents ________. |
A. | AND-OR logic |
B. | AOI logic |
C. | XOR gate |
D. | XNOR gate |
Answer» B. AOI logic | |
1454. |
To design a divide-by-200 counter using synchronous counters, two 4-bit counters could be cascaded together to form an 8-bit counter. |
A. | True |
B. | False |
Answer» B. False | |
1455. |
The output of this circuit is always ________. |
A. | 1 |
B. | 0 |
C. | A |
D. | <span style="text-decoration:overline">A</span> |
Answer» D. <span style="text-decoration:overline">A</span> | |
1456. |
An ALU is a multipurpose device capable of providing several different logic operations. |
A. | True |
B. | False |
Answer» B. False | |
1457. |
One of the first steps in any HDL project is to define its scope by naming each input and output. |
A. | True |
B. | False |
Answer» B. False | |
1458. |
In the stepper motor, the half-step sequence is used when ________. |
A. | less torque is needed |
B. | larger steps are desired |
C. | smaller steps are desirable |
D. | more torque is needed |
Answer» D. more torque is needed | |
1459. |
What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic? |
A. | The HCT series is faster. |
B. | The HCT series is slower. |
C. | The HCT series is input and output voltage compatible with TTL. |
D. | The HCT series is not input and output voltage compatible with TTL. |
Answer» D. The HCT series is not input and output voltage compatible with TTL. | |
1460. |
How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? |
A. | 1 |
B. | 2 |
C. | 4 |
D. | 8 |
Answer» D. 8 | |
1461. |
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? |
A. | A > B = 1, A < B = 0, A < B = 1 |
B. | A > B = 0, A < B = 1, A = B = 0 |
C. | A > B = 1, A < B = 0, A = B = 0 |
D. | A > B = 0, A < B = 1, A = B = 1 |
Answer» D. A > B = 0, A < B = 1, A = B = 1 | |
1462. |
A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong? |
A. | The output of the gate appears to be open. |
B. | The dim indication on the logic probe indicates that the supply voltage is probably low. |
C. | The dim indication is a result of a bad ground connection on the logic probe. |
D. | The gate may be a tristate device. |
Answer» B. The dim indication on the logic probe indicates that the supply voltage is probably low. | |
1463. |
Most people would prefer to use ________ over HDL. |
A. | graphic descriptions |
B. | functions |
C. | VHDL |
D. | AHDL |
Answer» B. functions | |
1464. |
Erasing or programming a flash memory device is a one-step operation. |
A. | True |
B. | False |
Answer» C. | |
1465. |
DRAM uses a cross-transistor configuration. |
A. | True |
B. | False |
Answer» C. | |
1466. |
Which is a mode of operation of the GAL16V8? |
A. | Simple mode |
B. | Complex mode |
C. | Registered mode |
D. | All of the above |
Answer» E. | |
1467. |
A NAND gate consists of an AND gate and an OR gate connected in series with each other. |
A. | True |
B. | False |
Answer» C. | |
1468. |
Solve this binary problem: 01000110 00001010 = |
A. | 0111 |
B. | 10011 |
C. | 1001 |
D. | 0011 |
Answer» B. 10011 | |
1469. |
Four subcategories of ASIC devices are available to create digital systems. These are PLDs, gate arrays, standard cells, and ________. |
A. | HCPLDs |
B. | full custom |
C. | GAL |
D. | FPLDs |
Answer» C. GAL | |
1470. |
When coming up with a strategy for dividing the overall project into manageable-size pieces one must ________. |
A. | name each input and output |
B. | fully understand how the device should operate |
C. | define successful completion of the project |
D. | know the nature of all the signals that interconnect all the pieces |
Answer» E. | |
1471. |
In a real project, the first step of definition often involves some ________ on the part of the project manager. |
A. | time |
B. | skill |
C. | research |
D. | management |
Answer» D. management | |
1472. |
The stepper motor HDL will ignore its counter inputs and pass control inputs directly to the output when set in mode ________. |
A. | 1 |
B. | 2 |
C. | 3 |
D. | 4 |
Answer» B. 2 | |
1473. |
The output of a basic 4-bit input digital-to-analog converter would be capable of outputting: |
A. | 16 different values of voltage or current that are not proportional to the input binary number |
B. | 16 different values of voltage or current that are proportional to the input binary number |
C. | 32 different values of voltage or current that are not proportional to the input binary number |
D. | 32 different values of voltage or current that are proportional to the input binary number |
Answer» C. 32 different values of voltage or current that are not proportional to the input binary number | |
1474. |
The following waveform pattern is for a(n) ________. |
A. | 2-input AND gate |
B. | 2-input OR gate |
C. | Exclusive-OR gate |
D. | None of the above |
Answer» B. 2-input OR gate | |
1475. |
The ASCII code is a special code that represents all alphanumeric data. |
A. | True |
B. | False |
Answer» B. False | |
1476. |
The simplified form of . |
A. | True |
B. | False |
Answer» B. False | |
1477. |
A group of 6 bits is also known as 1 byte. |
A. | True |
B. | False |
Answer» C. | |
1478. |
A 4-bit stairstep-ramp A/D converter has a clock frequency of 100 kHz and maximum input voltage of 10 V. |
A. | The maximum number of samples per second will be 6250. |
B. | The maximum sample rate will be 100,000 samples/second. |
C. | The minimum sample rate will be 6250 samples/second. |
D. | The minimum sample rate will be 100,000 samples/second. |
Answer» D. The minimum sample rate will be 100,000 samples/second. | |
1479. |
A LOW placed on the input of an inverter will produce a HIGH output. |
A. | True |
B. | False |
Answer» B. False | |
1480. |
In VHDL, the architecture declaration always begins with the ________ of variable signals or components that will be used in the concurrent description between BEGIN and END. |
A. | type |
B. | vectors |
C. | functions |
D. | declarations |
Answer» E. | |
1481. |
The NAND gate is an example of combinational logic. |
A. | True |
B. | False |
Answer» B. False | |
1482. |
When decimal numbers with several digits are to be added together using BCD adders ________. |
A. | a separated BCD adder is required for each digit position |
B. | the BCD adders must have the carry-outs grounded |
C. | the BCD's must be grouped in twos |
D. | full adders are also used |
Answer» B. the BCD adders must have the carry-outs grounded | |
1483. |
The binary adder circuit is designed to add ________ binary number(s) at a time. |
A. | 1 |
B. | 3 |
C. | 2 |
D. | 5 |
Answer» D. 5 | |
1484. |
The 74HC382 ALU can perform ________ operations. |
A. | 2 |
B. | 4 |
C. | 8 |
D. | 16 |
Answer» D. 16 | |
1485. |
Subtraction of the 2's-complement system actually involves the operation of ________. |
A. | multiplication |
B. | subtraction |
C. | addition |
D. | division |
Answer» D. division | |
1486. |
BCD arithmetic is performed using base 10 numbers. |
A. | True |
B. | False |
Answer» C. | |
1487. |
A full adder has a carry-in. |
A. | True |
B. | False |
Answer» B. False | |
1488. |
The greater the propagation delay, the higher the maximum frequency. |
A. | True |
B. | False |
Answer» C. | |
1489. |
The complement of 1 is 0. |
A. | True |
B. | False |
Answer» B. False | |
1490. |
The speed-power product provides a basis for the comparison of logic circuits when power dissipation and propagation delay are important considerations in the selection of the type of logic to be used. |
A. | True |
B. | False |
Answer» B. False | |
1491. |
The 74F-Fast TTL integrated-circuit fabrication technique uses reduced interdevice ________ to achieve reduced propagation delays. |
A. | noise |
B. | resistance |
C. | capacitance |
D. | inductance |
Answer» D. inductance | |
1492. |
ECL IC technology is faster than TTL technology. |
A. | True |
B. | False |
Answer» B. False | |
1493. |
Hexadecimal is a base 4 numbering system. |
A. | True |
B. | False |
Answer» C. | |
1494. |
The solution to the binary problem 00110110 00011111 is 00011000. |
A. | True |
B. | False |
Answer» C. | |
1495. |
Unused TTL inputs should be tied LOW. |
A. | True |
B. | False |
Answer» C. | |
1496. |
In a DIP the spacing between pins is typically ________. |
A. | 5 mils |
B. | 10 mils |
C. | 50 mils |
D. | 100 mils |
Answer» E. | |
1497. |
P-MOS and N-MOS ________. |
A. | represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate |
B. | are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC |
C. | represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers |
D. | None of the above are. |
Answer» B. are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC | |
1498. |
________ is about twice as fast as P-MOS. |
A. | CMOS |
B. | DMOS |
C. | MOD |
D. | N-MOS |
Answer» E. | |
1499. |
The output stage of a TTL gate is a special design called ________. |
A. | multiemitter |
B. | totem-pole |
C. | MSI |
D. | DIP |
Answer» C. MSI | |
1500. |
A ________ is a testing and troubleshooting tool that generates a short-duration pulse when manually activated, usually by depressing a push button. |
A. | cattle prod |
B. | jimmy rod |
C. | logic pulser |
D. | bilateral switch |
Answer» D. bilateral switch | |