In VHDL, the architecture declaration always begins with the ________ of variable signals or components that will be used in the concurrent description between BEGIN and END.

In VHDL, the architecture declaration always begins with the ________

1.	In VHDL, the architecture declaration always begins with the ________ of variable signals or components that will be used in the concurrent description between BEGIN and END.
A.	type
B.	vectors
C.	functions
D.	declarations
Answer» E.