MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 102 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Architecture knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
Logic gates with a set of input and outputs is arrangement of |
| A. | Combinational circuit |
| B. | Logic circuit |
| C. | Design circuits |
| D. | Register |
| Answer» B. Logic circuit | |
| 52. |
An n-bit register has a group of n flip-flops and some |
| A. | Logic Gates |
| B. | Registers |
| C. | ROM |
| D. | None of the above |
| Answer» B. Registers | |
| 53. |
Gated S-R latch is a combination of which latch and gate? |
| A. | J-K latch and NOR gate |
| B. | S-R latch and NAND gate |
| C. | S-R latch and NOR gate |
| D. | J-K latch and NAND gate |
| Answer» C. S-R latch and NOR gate | |
| 54. |
Memory can be classified on the basis of the ______________ technology used. |
| A. | Non- Fabrication |
| B. | Bipolar |
| C. | Fabrication |
| D. | None of the above |
| Answer» D. None of the above | |
| 55. |
Data can be changed from special code to temporal code by using |
| A. | Shift registers |
| B. | counters |
| C. | Combinational circuits |
| D. | A/D converters |
| Answer» B. counters | |
| 56. |
A register used to provide data movements |
| A. | Parallel Register |
| B. | Simple Register |
| C. | Shift Register |
| D. | All of the above |
| Answer» D. All of the above | |
| 57. |
The gates required to build a half adder are |
| A. | EX-OR gate and NOR gate |
| B. | EX-OR gate and OR gate |
| C. | EX-OR gate and AND gate |
| D. | Four NAND gates |
| Answer» D. Four NAND gates | |
| 58. |
A register that can be either static or dynamic |
| A. | Shift |
| B. | Parallel |
| C. | Bit |
| D. | None of the above |
| Answer» B. Parallel | |
| 59. |
It is a circuit, which subtracts two inputs each of one bit |
| A. | Full Subtractor |
| B. | Full Adder |
| C. | Half Subtractor |
| D. | All of the above |
| Answer» D. All of the above | |
| 60. |
In a DAC, the possible number of digital input is __________. |
| A. | Fixed |
| B. | Not fixed |
| C. | 4 |
| D. | 2 |
| Answer» B. Not fixed | |
| 61. |
Memory is a circuit, which is used to store ____________ information. |
| A. | Accurate |
| B. | Discrete |
| C. | Analog |
| D. | Digital |
| Answer» E. | |
| 62. |
In a combinational circuit, each output depends entirely on the ________ inputs to the circuit. |
| A. | Same |
| B. | Different |
| C. | Common |
| D. | Immediate |
| Answer» E. | |
| 63. |
Circuits that are more complex can be built using the __________ method. |
| A. | First- level |
| B. | Digital Level |
| C. | Block Level |
| D. | None of the above |
| Answer» D. None of the above | |
| 64. |
If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is |
| A. | 1000 Hz |
| B. | 500 Hz |
| C. | 333 Hz |
| D. | 12.5 Hz |
| Answer» E. | |
| 65. |
BCD-to-Excess-3 Code Conversion is a example of a ______________. |
| A. | 4-bit Parallel Adder |
| B. | Sum-of-Products |
| C. | 2- bit Parallel Adder |
| D. | None of the above |
| Answer» B. Sum-of-Products | |
| 66. |
A basic AND gate consists of ______________inputs and an output. |
| A. | One |
| B. | Zero |
| C. | Two |
| D. | Ten |
| Answer» D. Ten | |
| 67. |
It is a simple combinational digital circuit built from logic gates |
| A. | Full Adder |
| B. | Half Adder |
| C. | Null Adder |
| D. | None of the above |
| Answer» C. Null Adder | |
| 68. |
A ________________ circuit is not suitable in the synchronous circuit design because of its transparency nature. |
| A. | Latch |
| B. | Parallel |
| C. | Diagonal Circuit |
| D. | None of the above |
| Answer» B. Parallel | |
| 69. |
In flip-flop, the ___________ arrow shows positive transition on the clock. |
| A. | Upward |
| B. | Downward |
| C. | Vertical |
| D. | Horizontal |
| Answer» B. Downward | |
| 70. |
A flip-flop is a binary cell capable of storing information of |
| A. | One bit |
| B. | Byte |
| C. | Zero bit |
| D. | Eight bit |
| Answer» B. Byte | |
| 71. |
A device/circuit that goes through a predefined sequence of states upon the application of input pulses is called |
| A. | register |
| B. | flip-flop |
| C. | transistor |
| D. | counter |
| Answer» E. | |
| 72. |
The number of control lines for 16 to 1 multiplexer is |
| A. | 2 |
| B. | 4 |
| C. | 3 |
| D. | 5 |
| Answer» C. 3 | |
| 73. |
Words having 8-bits are to be stored into computer memory. The number of lines required for writing into memory are |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» E. | |
| 74. |
It is a single input version of J-K flip-flop formed by tying both the inputs of J-K. |
| A. | D flip-flop |
| B. | S flip-flop |
| C. | T flip-flop |
| D. | N flip-flop |
| Answer» D. N flip-flop | |
| 75. |
It does not have any external gate. |
| A. | Simple Register |
| B. | Buffers |
| C. | Memory |
| D. | RAM |
| Answer» B. Buffers | |
| 76. |
How many flip flops are required to construct a decade counter |
| A. | 10 |
| B. | 3 |
| C. | 4 |
| D. | 2 |
| Answer» D. 2 | |
| 77. |
In this logic, output depends not only on the current inputs but also on the past input values. It needs some type of memory to remember the past input values |
| A. | Logical Circuit |
| B. | Connected Circuit |
| C. | Sequential Circuit |
| D. | Parallel Circuit |
| Answer» D. Parallel Circuit | |
| 78. |
'n' Flip flops will divide the clock frequency by a factor of |
| A. | n^2 |
| B. | n |
| C. | 2^n |
| D. | log (n) |
| Answer» C. 2^n | |
| 79. |
It is a circuit, which has a number of input lines and selection lines with one output line. |
| A. | Sequential Circuit |
| B. | Multiplexer |
| C. | Counter |
| D. | All of the above |
| Answer» C. Counter | |
| 80. |
There are________________ basic types of flip-flop based on clock trigger. |
| A. | 2 |
| B. | 6 |
| C. | 8 |
| D. | 4 |
| Answer» E. | |
| 81. |
A _________________ is a circuit, which can remember values for a long time or change values when required. |
| A. | Logical Circuit |
| B. | Digital Circuit |
| C. | Memory Element |
| D. | Complex Circuit |
| Answer» D. Complex Circuit | |
| 82. |
Advantage of synchronous sequential circuits over asynchronous ones is |
| A. | faster operation |
| B. | ease of avoiding problems due to hazard |
| C. | lower hardware requirement |
| D. | better noise immunity |
| Answer» B. ease of avoiding problems due to hazard | |
| 83. |
How many flip-flops are required to construct mod 30 counter |
| A. | 5 |
| B. | 6 |
| C. | 4 |
| D. | 8 |
| Answer» B. 6 | |
| 84. |
Which of following consume minimum power? |
| A. | TTL |
| B. | CMOS |
| C. | DTL |
| D. | RTL |
| Answer» C. DTL | |
| 85. |
It is a counter where the flip-flops do not change states at exactly the same time, as they do not have a common clock pulse. |
| A. | Asynchronous Ripple Counter |
| B. | Synchronous Ripple Counter |
| C. | Counter |
| D. | All of the above |
| Answer» B. Synchronous Ripple Counter | |
| 86. |
The major block(s) of the dual- slope ADC |
| A. | Integrator |
| B. | Comparator |
| C. | Binary counter, switch drive |
| D. | All of the above |
| Answer» E. | |
| 87. |
A counter with 10 states |
| A. | Cascading asynchronous counter |
| B. | Decade counter |
| C. | Asynchronous ripple counter |
| D. | Ripple counter |
| Answer» C. Asynchronous ripple counter | |
| 88. |
The four common and useful MSI circuits are |
| A. | Decoder |
| B. | Demultiplexer |
| C. | Encoder |
| D. | All of the above |
| Answer» E. | |
| 89. |
How many select lines will a 32:1 multiplexer will have |
| A. | 5 |
| B. | 8 |
| C. | 9 |
| D. | 11 |
| Answer» B. 8 | |
| 90. |
The total current can be converted into the corresponding voltage by using a/an _______________. |
| A. | Op-Amp |
| B. | Binary weighted ladder |
| C. | Delta sigma DAC |
| D. | Hybrid DAC |
| Answer» B. Binary weighted ladder | |
| 91. |
The MSI chip 7474 is |
| A. | Dual edge triggered JK flip-flop (TTL) |
| B. | Dual edge triggered D flip-flop (CMOS) |
| C. | Dual edge triggered D flip-flop (TTL) |
| D. | Dual edge triggered JK flip-flop (CMOS) |
| Answer» D. Dual edge triggered JK flip-flop (CMOS) | |
| 92. |
The characteristics of a DAC, which are generally specified by the manufacturers |
| A. | Linearity |
| B. | Resolution |
| C. | Accuracy |
| D. | All of the above |
| Answer» E. | |
| 93. |
The operation which commutative but not associative is |
| A. | AND |
| B. | OR |
| C. | XOR |
| D. | NAND |
| Answer» E. | |
| 94. |
A NAND gate has inputs A and B. It's output is connected to the both of the inputs of another NAND gate. An equivalent gate for these two NAND gates is |
| A. | OR gate |
| B. | AND gate |
| C. | NOR gate |
| D. | XOR gate |
| Answer» C. NOR gate | |
| 95. |
CARRY in half adder can be obtained using |
| A. | EX-OR gate |
| B. | AND gate |
| C. | OR-gate |
| D. | EX-NOR gate |
| Answer» C. OR-gate | |
| 96. |
Which of the following is not a universal building block ? |
| A. | 2 input NAND gate |
| B. | L3 input NAND gate |
| C. | 2 input XOR gate |
| D. | None of the above |
| Answer» D. None of the above | |
| 97. |
An adder-subtractor single unit can be designed using full adder and |
| A. | OR gates |
| B. | XOR gates |
| C. | NOR gates |
| D. | NAND gates |
| Answer» C. NOR gates | |
| 98. |
The basic circuit ECL supports the |
| A. | NAND logic |
| B. | NOR logic |
| C. | EX-OR logic |
| D. | OR-NOR logic |
| Answer» E. | |
| 99. |
BCD stands for |
| A. | Boolean code definition |
| B. | Binary coded division |
| C. | Binary coded decimal |
| D. | None of the above |
| Answer» D. None of the above | |
| 100. |
Normally digital computers are based on |
| A. | AND and OR gates |
| B. | NAND and NOR gates |
| C. | NOT gate |
| D. | None of the above |
| Answer» C. NOT gate | |