MCQOPTIONS
Saved Bookmarks
MCQOPTIONS
This section includes 63 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The state transition given below is realized by a clocked JK FF.
The JK input to realize the transition is |
||||||||||||
| A. | |||||||||||||
| B. | |||||||||||||
| C. | |||||||||||||
| Answer» B. | |||||||||||||
| 2. |
The octal equivalent of the HEX number AB.CD is |
| A. | 253.314 |
| B. | 253.632 |
| C. | 526.314 |
| D. | 526.632 |
| Answer» C. 526.314 | |
| 3. |
A mod-2 counter followed by a mod-5 counter is |
| A. | same as a mode-5 counter followed by a mod- 2 counter |
| B. | a decade counter |
| C. | a mod-7 counter |
| D. | none of these |
| Answer» B. a decade counter | |
| 4. |
The output Qn of a J-K flip-flop is zero. It change to 1 when a clock pulse is applied. The input Jn and Kn are respectively |
| A. | 1 and X |
| B. | 0 and X |
| C. | X and 0 |
| D. | X and 1 |
| Answer» B. 0 and X | |
| 5. |
A 5 bit D/A converter has a current output for a digital input of 10100. If an output current of 10 m A is produced, what will Iout be for a digital input of 11101? |
| A. | 12.5 mA |
| B. | 13.5 mA |
| C. | 14.5 mA |
| D. | 15.5 mA |
| Answer» D. 15.5 mA | |
| 6. |
For a MOD-12 counter, FF hasa tpd = 60 ns. NAND gate has a tpd of 25 ns. The clock frequency is |
| A. | = 3.774 MHz |
| B. | > 3.774 MHz |
| C. | < 3.774 MHz |
| D. | = 4.167 MHz |
| Answer» B. > 3.774 MHz | |
| 7. |
Assuming that only X and Y logic inputs are available and their complements X and Y are not available, then what is the minimum number of two-input nand gates require to implement X Y? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 8. |
The minimum number of NAND gates required to implement A + AB + ABC is equal to |
| A. | zero |
| B. | 1 |
| C. | 4 |
| D. | 7 |
| Answer» B. 1 | |
| 9. |
An 8-bi t di gi t al -r amp ADC wi t h a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with VT = 1mV. The digital output for VA = 6.000 V is |
| A. | 1 0 0 1 0 1 1 1 |
| B. | 1 0 0 1 0 1 1 0 |
| C. | 1 0 1 1 1 1 0 |
| D. | 1 0 1 1 1 1 1 |
| Answer» B. 1 0 0 1 0 1 1 0 | |
| 10. |
The increasing order of speed of data access for the following devices is
|
| A. | (v), (ii), (iii), (iv), (i) |
| B. | (v), (ii), (iii), (i), (iv) |
| C. | (ii), (i), (iii), (iv), (v) |
| D. | (v), (ii), (i), (iii), (iv) |
| Answer» C. (ii), (i), (iii), (iv), (v) | |
| 11. |
Venn diagram representing the Boolean expression A + (A. B) is |
| A. | |
| Answer» B. | |
| 12. |
Consider the following expressions
|
| A. | 2 and 3 |
| B. | 1 and 4 |
| C. | 2 and 4 |
| D. | 1 and 3 |
| Answer» E. | |
| 13. |
A 5 bit D/A converter has a current output for a digital input of 10100. If an output current of 10 m A is produced, what will I |
| A. | 12.5 mA |
| B. | 13.5 mA |
| C. | 14.5 mA |
| D. | 15.5 mA |
| Answer» D. 15.5 mA | |
| 14. |
What overall accuracy could one reasonably expect from construction of a 10 bit A/D converter? |
| A. | 0.1% |
| B. | 0.2% |
| C. | 0.3% |
| D. | 0.4% |
| Answer» C. 0.3% | |
| 15. |
The simplified block diagram of a 10-bi t A/D converter of dual slope integrator type is shown in the given figure. The 10-bit counter at the output is clocked by a 1 MHz clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this A/D converter is approximately _________kHz |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 5 |
| Answer» B. 2 | |
| 16. |
For a dual ADC type 3 1/2 digit DVM, reference voltage is 100 mV and first integration time is set to 300 ms. For some input voltage, deintegration period is 370.2 ms. The DVM will indicate ____________. |
| A. | 199.9 |
| B. | 200 |
| C. | 198.8 |
| D. | 125.12 |
| Answer» B. 200 | |
| 17. |
In a 4-bit weighted resistor D/A converter, the resistor value corresponding to LSB is 32-k ohm. The resistor value corresponding to MSB will be _________k |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 18. |
An analog voltage is in the range of 0 to 8 V is divided in eight equal intervals for conversion to 3-bit digital output. The maximum quantization error is _________V |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 19. |
A JK flip flop can be implemented by T flip-flops. Identify the correct implementation. |
| A. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-10A.png"> |
| B. | |
| C. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-10B.png"> |
| D. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-10C.png"> |
| E. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-10D.png"> |
| Answer» C. <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-10B.png"> | |
| 20. |
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is |
| A. | 4 |
| B. | 6 |
| C. | 8 |
| D. | 10 |
| Answer» C. 8 | |
| 21. |
Assuming that only X and Y logic inputs are available and their complements |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 22. |
The dual of the Boolean theorem A. (B + C) = A.B + A.C is |
| A. | A + (B + C) = A.B + A.C |
| B. | A. (B + C) = (A + B) (A + C) |
| C. | A + B.C = (A + B) (A + C) |
| D. | None of these |
| Answer» D. None of these | |
| 23. |
The Q output of a J K flip-flop is 1 . The output does not change when a clock-pulse is applied.The inputs J and K will be respectively (X-denotes don t care state) |
| A. | 0 and X |
| B. | X and 0 |
| C. | 1 and 0 |
| D. | 0 and 1. |
| Answer» C. 1 and 0 | |
| 24. |
The octal equivalent of the HEX number |
| A. | 253.314 |
| B. | 253.632 |
| C. | 526.314 |
| D. | 526.632 |
| Answer» C. 526.314 | |
| 25. |
In a 4 bit counter, the outputs of 3 JK FFs from MSB downward are connected to the NAND gate whose output is connected to CLR. |
| A. | It is a MOD-14 counter |
| B. | It is a MOD-13 counter |
| C. | It is a divide by-13 counter |
| D. | It is a divide by-14 counter |
| Answer» E. | |
| 26. |
If a counter having 10 FFs is initially at 0, what count will if hold after 2060 pulses? |
| A. | 000 000 1100 |
| B. | 000 001 1100 |
| C. | 000 001 1000 |
| D. | 000 000 1110 |
| Answer» B. 000 001 1100 | |
| 27. |
The output Q |
| A. | 1 and X |
| B. | 0 and X |
| C. | X and 0 |
| D. | X and 1 |
| Answer» B. 0 and X | |
| 28. |
Which of the following is an invalid state in an 8-4-2-1 Binary Coded Decimal counter |
| A. | 1000 |
| B. | 1001 |
| C. | 0011 |
| D. | 1100 |
| Answer» E. | |
| 29. |
A 10 bit A/D converter is used to digitise an analog signal in the 0 to 5 V range. The maximum peak to peak ripple voltage that can be allowed in the d.c. supply voltage is |
| A. | nearly 100 mV |
| B. | nearly 50 mV |
| C. | nearly 25 mV |
| D. | nearly 5.0 mV |
| Answer» E. | |
| 30. |
For a MOD-12 counter, FF hasa t |
| A. | = 3.774 MHz |
| B. | > 3.774 MHz |
| C. | < 3.774 MHz |
| D. | = 4.167 MHz |
| Answer» B. > 3.774 MHz | |
| 31. |
A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1 sec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/ H circuit is 5V. The leakage current of the S/H circuit should be less than _____________ A |
| A. | 4.5 |
| B. | 5.5 |
| C. | 3.5 |
| D. | 2.5 |
| Answer» E. | |
| 32. |
A 4-bit preset table UP counter has preset input 0101. The preset operation takes place as soon as the counter becomes maximum 1111.The modulus of the counter is |
| A. | 5 |
| B. | 10 |
| C. | 11 |
| D. | 15 |
| Answer» C. 11 | |
| 33. |
A 4 bit ripple counter and a 4 bit synchronous counter are made by flips flops having a propagation delay of 10 ns each. If worst case delay in the ripple counter and the synchronous counter be R and S respectively, then |
| A. | R = 10 ns, S = 40 ns |
| B. | R = 40 ns, S = 10 ns |
| C. | R = 10 ns, S = 30 ns |
| D. | R = 30 ns, S = 10 ns |
| Answer» C. R = 10 ns, S = 30 ns | |
| 34. |
A pulse train can be delayed by a finite number periods usings of clock |
| A. | a serial in serial shift register |
| B. | a serial in parallel out shift register |
| C. | a parallel in serial out shift register |
| D. | a serial in parallel out shift register |
| Answer» B. a serial in parallel out shift register | |
| 35. |
A retriggerable monoshot is one which |
| A. | can be triggered only once |
| B. | has two quasi-stable states |
| C. | cannot be triggered until full pulse has been |
| D. | is capable of being triggered while the output is being |
| Answer» E. | |
| 36. |
A sequential multiplexer is connected as shown in the figure. Each time the multiplexer receivers the clock, it switches to the next cannel (from 6 it goes to 1) if input signals are |
| A. | 5 cos (2 (4 10 t) |
| B. | 2 cos 2 (3.8 10 t) |
| C. | 6 cos 2 (2.2 10 t) |
| D. | 4 cos 2 (17 10 t) |
| Answer» E. | |
| 37. |
In time devision multiplexing |
| A. | time is doubled between bits of a byte |
| B. | time slicing at CPU level takes place |
| C. | total time available in the channel is divided bet ween sever al user s and each user s is allotted a time slice |
| D. | none of these |
| Answer» D. none of these | |
| 38. |
How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T flip-flops? Assume unlimited fan-in. |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 1 |
| Answer» D. 1 | |
| 39. |
12 MHz clock frequency is applied to a cascaded counter of modulus-3 counter, modulus-4 counter and modulus-5 counter. What are the lowest out put frequency and the over all modulus, respectively? |
| A. | 200 kHz, 60 |
| B. | 1 MHz, 60 |
| C. | 3 MHz, 12 |
| D. | 4 MHz, 12 |
| Answer» B. 1 MHz, 60 | |
| 40. |
The address bus width of a memory of size 1024 8 bits is |
| A. | 10 bits |
| B. | 13 bits |
| C. | 8 bits |
| D. | 18 bits |
| Answer» B. 13 bits | |
| 41. |
Four memory chips of 16 4 size have their address buses connected together. This system will be of size |
| A. | 64 4 |
| B. | 32 8 |
| C. | 16 16 |
| D. | 256 1 |
| Answer» D. 256 1 | |
| 42. |
A pulse train with a frequency of 1 MHz is counted using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per flip-flop stage is |
| A. | 100 n sec |
| B. | 50 n sec |
| C. | 20 n sec |
| D. | 10 n sec |
| Answer» B. 50 n sec | |
| 43. |
In a sequential circuit, the outputs at anyinstant of time depends |
| A. | only on the inputs present at that instant of time |
| B. | on past outputs as well as present inputs |
| C. | only on the past inputs |
| D. | only on the present outputs |
| Answer» C. only on the past inputs | |
| 44. |
Metastability in D-Flip Flop occurs when |
| A. | set up time of input data is not met |
| B. | clock period is too large |
| C. | set and reset are active simultaneously |
| D. | D and Q pins are shortened. |
| Answer» B. clock period is too large | |
| 45. |
A 4 bit modulo 16 ripple counter used JK flipflop. If progression delay of each FF is 50 ms, then maximum clock frequency is equal to |
| A. | 20 MHz |
| B. | 10 MHz |
| C. | 5 MHz |
| D. | 4 MHz |
| Answer» D. 4 MHz | |
| 46. |
A switch-tail ring counter is made by using a single D-FF. The resulting ciruit is |
| A. | SR flip-flop |
| B. | JK flip-flop |
| C. | D FF |
| D. | T FF |
| Answer» E. | |
| 47. |
A 4-bit-synchronous counter uses flip-flops with pr opagation delay time of 25 ns each. The maximum possible time required for change of state will be |
| A. | 25 ns |
| B. | 50 ns |
| C. | 75 ns |
| D. | 100 ns |
| Answer» B. 50 ns | |
| 48. |
A 12 bit ADC is operating with a 1 sec clock period and total conversion time is seen to be 14 secs. The ADC must to be of the |
| A. | flash type |
| B. | counting type |
| C. | integrating type |
| D. | successive approximation type |
| Answer» E. | |
| 49. |
If resolution of a D/A converter is approximately 0.4% of its full-scale range. then it is a/an |
| A. | 8 bit converter |
| B. | 10 bit converter |
| C. | 12 bit converter |
| D. | 16 bit converter |
| Answer» B. 10 bit converter | |
| 50. |
Among the following, the slowest ADC (Analogto-digital converter) is |
| A. | parallel-comparator (i.e. flash) type |
| B. | successive approximation type |
| C. | integrating type |
| D. | counting type |
| Answer» C. integrating type | |