MCQOPTIONS
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MCQOPTIONS
This section includes 63 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 51. |
An 8-bi t di gi t al -r amp ADC wi t h a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with V |
| A. | 1 0 0 1 0 1 1 1 |
| B. | 1 0 0 1 0 1 1 0 |
| C. | 1 0 1 1 1 1 0 |
| D. | 1 0 1 1 1 1 1 |
| Answer» B. 1 0 0 1 0 1 1 0 | |
| 52. |
The number of comparator sin a parallel conversion type 8-bit A to D converter is ____________. |
| A. | 256 |
| B. | 255 |
| C. | 245 |
| D. | 256 |
| Answer» C. 245 | |
| 53. |
A 4 bit modulo-6 ripple counter uses JK flip-flop. If propagation delay of each FF is 50 ns, then maximum clock frequency that can be used is equal to _________MHz |
| A. | 1 |
| B. | 3 |
| C. | 7 |
| D. | 5 |
| Answer» E. | |
| 54. |
A memory system has a total of 8 memory chips, each with 12 address lines and 4 data lines. The total size of the memory system is __________kB |
| A. | 31 |
| B. | 32 |
| C. | 68 |
| D. | 33 |
| Answer» C. 68 | |
| 55. |
The output of a logic gate is 1 when all its inputs are at logic 0 . The gate is either |
| A. | NAND or EX-OR gate |
| B. | NOR or EX-NOR gate |
| C. | OR or EX-NOR gate |
| D. | AND or EX-OR gate |
| Answer» C. OR or EX-NOR gate | |
| 56. |
Venn diagram representing the Boolean expression A + ( |
| A. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-15A.png"> |
| B. | |
| C. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-15B.png"> |
| D. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-15C.png"> |
| E. | <img src="http://images.interviewmania.com/wp-content/uploads/2019/12/Q-15D.png"> |
| Answer» B. | |
| 57. |
The minimum number of NAND gates required to implement A + A |
| A. | zero |
| B. | 1 |
| C. | 4 |
| D. | 7 |
| Answer» B. 1 | |
| 58. |
The complete set of only those Logic Gates designated as Universal gates is |
| A. | NOT, OR and AND Gates |
| B. | XNOR, NOR and NAND Gates |
| C. | NOR and NAND Gates |
| D. | XOR, NOR and NAND Gates |
| Answer» D. XOR, NOR and NAND Gates | |
| 59. |
A dual trace oscilloscope is set to operate in the ALTernate mode. The control input of the multiplexer used in the y-circuit is fed with a signal having a frequency equal to |
| A. | the highest frequency that the multiplexer can operate properly |
| B. | twice the frequency of the time base (sweep) oscillator |
| C. | the frequency of the time base (sweep) oscillator |
| D. | half the frequency of the time base (sweep) oscillator |
| Answer» D. half the frequency of the time base (sweep) oscillator | |
| 60. |
The increasing order of speed of data access for the following devices is |
| A. | (v), (ii), (iii), (iv), (i) |
| B. | (v), (ii), (iii), (i), (iv) |
| C. | (ii), (i), (iii), (iv), (v) |
| D. | (v), (ii), (i), (iii), (iv) |
| Answer» C. (ii), (i), (iii), (iv), (v) | |
| 61. |
When signed numbers are used in binary arithmetic, then which of the following notations would have unique representation for zero? |
| A. | Sign-magnitude |
| B. | 1 s complement |
| C. | 2 s complement |
| D. | 9 s complement |
| Answer» D. 9 s complement | |
| 62. |
Consider the following expressions |
| A. | 2 and 3 |
| B. | 1 and 4 |
| C. | 2 and 4 |
| D. | 1 and 3 |
| Answer» E. | |
| 63. |
A full-adder can be implemented with half-adders and OR gates. A 4-bit parallel full adder without any initial carry requires |
| A. | 8 half-adders,4-OR gates |
| B. | 8 half-adders, 3-OR gates |
| C. | 7 half-adders, 4-OR gates |
| D. | 7 half-adders, 3-OR gates |
| Answer» E. | |