The simplified block diagram of a 10-bi t A/D converter of dual slope – McqOptions

MCQOPTIONS

1.	The simplified block diagram of a 10-bi t A/D converter of dual slope integrator type is shown in the given figure. The 10-bit counter at the output is clocked by a 1 MHz clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this A/D converter is approximately _________kHz
A.	1
B.	2
C.	3
D.	5
Answer» B. 2

Discussion

No Comment Found

Related MCQs

The state transition given below is realized by a clocked JK FF. <br><table><tr><th>State</th><th>Transition</th></tr><tr><td>Q<sub>n</sub></td><td>Q<sub>n+1</sub></td></tr><tr><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td></tr><br><tr><td>1</td><td>0</td></tr><tr><td>1</td><td>1</td></tr></table><br>The JK input to realize the transition is
The octal equivalent of the HEX number <b>AB.CD</b> is
A mod-2 counter followed by a mod-5 counter is
The output Q<sub>n</sub> of a J-K flip-flop is zero. It change to 1 when a clock pulse is applied. The input J<sub>n</sub> and K<sub>n</sub> are respectively
A 5 bit D/A converter has a current output for a digital input of 10100. If an output current of 10 m A is produced, what will I<sub>out</sub> be for a digital input of 11101?
For a MOD-12 counter, FF hasa t<sub>pd</sub> = 60 ns. NAND gate has a t<sub>pd</sub> of 25 ns. The clock frequency is
Assuming that only X and Y logic inputs are available and their complements <span style=" text-decoration: overline;">X</span> and <span style=" text-decoration: overline;">Y</span> are not available, then what is the minimum number of two-input nand gates require to implement X Y?
The minimum number of NAND gates required to implement A + A<span style=" text-decoration: overline;">B</span> + A<span style=" text-decoration: overline;">B</span>C is equal to
An 8-bi t di gi t al -r amp ADC wi t h a 40 mV resolution uses a clock frequency of 2.5 MHz and a comparator with V<sub>T</sub> = 1mV. The digital output for VA = 6.000 V is
The increasing order of speed of data access for the following devices is <br>(i) Cache Memory<br>(ii) CDROM <br>(iii) Dynamic RAM <br>(iv) Processor Registers <br>(v) Magnetic Tape <br>Codes: