MCQOPTIONS
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MCQOPTIONS
This section includes 13 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Access types are similar to _________ in traditional programming languages. |
| A. | Pointers |
| B. | Arrays |
| C. | Structures |
| D. | Files |
| Answer» B. Arrays | |
| 2. |
What is the difference between SIGNAL and VARIABLE? |
| A. | The value of SIGNAL never varies whereas VARIABLE can change its value |
| B. | SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals |
| C. | SIGNAL depends upon VARIABLE for various operations |
| D. | SIGNAL is global and VARIABLE is local to the process in which it is declared |
| Answer» E. | |
| 3. |
RECORD in VHDL is similar to________ in C. |
| A. | Array |
| B. | File |
| C. | Structure |
| D. | Pointer |
| Answer» D. Pointer | |
| 4. |
Multidimensional arrays can be used for the implementation of memories. |
| A. | True. |
| B. | False. |
| Answer» B. False. | |
| 5. |
SIGNAL a : REAL; which of the following is illegal assignment for a? |
| A. | a <= 1.8 |
| B. | a <= 1.0 E10 |
| C. | a <= 1.0 E-10 |
| D. | a <=1.0 ns |
| Answer» E. | |
| 6. |
Which of the following is only predefined physical literal in VHDL? |
| A. | VOLTAGE |
| B. | TIME |
| C. | CURRENT |
| D. | DISTANCE |
| Answer» C. CURRENT | |
| 7. |
What is the meaning of the base unit? |
| A. | Smallest possible unit of any physical literal |
| B. | SI unit of any physical literal |
| C. | CGS unit for any physical literal |
| D. | Fundamental building block of any design |
| Answer» B. SI unit of any physical literal | |
| 8. |
What do we call the data type used for representing distance, current, voltage, time, etc? |
| A. | Integer |
| B. | Real |
| C. | Physical |
| D. | Imaginary |
| Answer» D. Imaginary | |
| 9. |
If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is? |
| A. | x <= a.b |
| B. | x <= a OR b |
| C. | x <= a + b |
| D. | x <= a && b |
| Answer» C. x <= a + b | |
| 10. |
Which of the following option is completely legal, given that a and b are two UNSIGNED type signals? |
| A. | x <= a + b; y <= a b; |
| B. | x <= a OR b; y <= a AND b; |
| C. | x <= a + b; y <= a OR b; |
| D. | x <= a OR b; y <= a + b; |
| Answer» B. x <= a OR b; y <= a AND b; | |
| 11. |
An UNSIGNED type is always greater than zero. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 12. |
What is the correct method to declare a SIGNED type signal x ? |
| A. | SIGNAL x : IN SIGNED |
| B. | SIGNAL x : IN SIGNED |
| C. | SIGNAL x : IN SIGNED (7 DOWNTO 0) |
| D. | SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0) |
| Answer» D. SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0) | |
| 13. |
SIGNED and UNSIGNED data types are defined in which package? |
| A. | std_logic_1164 package |
| B. | std_logic package |
| C. | std_logic_arith package |
| D. | standard package |
| Answer» D. standard package | |