Explore topic-wise MCQs in Computer Organization.

This section includes 585 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.

351.

__ provides a seperate physical connection to the memory.

A. PCI BUS
B. PCI interface
C. PCI bridge
D. Switch circuit
Answer» D. Switch circuit
352.

PCI stands for ____

A. Peripheral Component Interconnect
B. Peripheral Computer Internet
C. Processor Computer Interconnect
D. Processor Cable Interconnect
Answer» B. Peripheral Computer Internet
353.

In serial port interface, the INTR line is connected to _

A. Status register
B. Shift register
C. Shift register
D. None of the mentioned
Answer» B. Shift register
354.

The ______ is the BUS used in Macintosh PC’s.

A. NuBUS
B. EISA
C. PCI
D. None of the mentioned
Answer» B. EISA
355.

The key feature of the PCI BUS is

A. Low cost connectivity
B. Plug and Play capability
C. Expansion of Bandwidth
D. None of the mentioned
Answer» C. Expansion of Bandwidth
356.

The PCI follows a set of standards primarily used in _____ PC’s.

A. Intel
B. Motorola`
C. IBM
D. SUN
Answer» D. SUN
357.

The standard used in serial ports to facilitate communication is _____

A. RS-246
B. RS-LNK
C. RS-232-C
D. Both RS-246 and RS-LNK
Answer» D. Both RS-246 and RS-LNK
358.

The data transfer in UART is done in _

A. Asynchronous start stop format
B. Synchrnous start stop format
C. Isochronous format
D. EBDIC format
Answer» B. Synchrnous start stop format
359.

The key feature of UART is

A. Its architectural design
B. Its simple implementation
C. Its general purpose usage
D. Its enhancement of connecting low speed devices
Answer» E.
360.

UART stands for ____

A. Universal Asynchronous Relay Transmission
B. Universal Accumulator Register Transfer
C. Universal Asynchronous Receiver Transmitter
D. None of the mentioned
Answer» D. None of the mentioned
361.

_____ to increase the flexibility of the serial ports.

A. The wires used for ports is changed
B. The ports are made to allow different clock signals for input and output
C. The drivers are modified
D. All of the mentioned
Answer» C. The drivers are modified
362.

The double buffer is used for

A. Enabling receival of multiple bits of input
B. Combining the input and output operations
C. Extending the buffer capacity
D. None of the mentioned
Answer» B. Combining the input and output operations
363.

The transformation between the Parallel and serial ports is done with the help of _

A. Flip flops
B. Logic circuits
C. Shift registers
D. None of the mentioned
Answer» D. None of the mentioned
364.

The mode of transmission of data, where one bit is sent for each clock cycle is ____

A. Asynchronous
B. Parallel
C. Serial
D. Isochronous
Answer» E.
365.

In a general 8-bit parallel interface, the INTR line is connected to _____

A. Status and Control unit
B. DDR
C. Register select
D. None of the mentioned
Answer» B. DDR
366.

In the output interface of the parallel port, along with the valid signal ______ is also sent.

A. Data
B. Idle signal
C. Interrupt
D. Acknowledge signal
Answer» C. Interrupt
367.

DDR stands for __

A. Data Direction Register
B. Data Decoding Register
C. Data Decoding Rate
D. None of the mentioned
Answer» B. Data Decoding Register
368.

The Status flag circuit is implemented using __

A. RS flip flop
B. D flip flop
C. JK flip flop
D. Xor circuit
Answer» C. JK flip flop
369.

The disadvantage of using parallel mode of communication is ___

A. It is costly
B. Leads to erroneous data transfer
C. Security of data
D. All of the mentioned
Answer» B. Leads to erroneous data transfer
370.

The best mode of conncetion between devices which need to send or recieve large amounts of data over a short distance is __

A. BUS
B. Serial port
C. Parallel port
D. Isochronous port
Answer» D. Isochronous port
371.

To overcome multiple signals being generated upon a single press of the button, we make use of ___

A. Generator circuit
B. Debouncing circuit
C. Multiplexer
D. XOR circuit
Answer» C. Multiplexer
372.

The output of the encoder circuit is/are __

A. ASCII code
B. ASCII code and the valid signal
C. Encoded signal
D. None of the mentioned
Answer» C. Encoded signal
373.

IDE stands for ____

A. Intergrated Device Electronics
B. International Device Encoding
C. Industrial Decoder Electronics
D. International Decoder Encoder
Answer» B. International Device Encoding
374.

The _____ circuit enables the generation of the ASCII code when the key is pressed.

A. Generator
B. Debouncing
C. Encoder
D. Logger
Answer» D. Logger
375.

The system developed by IBM with ISA architecture is _

A. SPARC
B. SUN-SPARC
C. PC-AT
D. None of the mentioned
Answer» D. None of the mentioned
376.

IDE disk is connected to the PCI BUS using ______ interface.

A. ISA
B. ISO
C. ANSI
D. IEEE
Answer» B. ISO
377.

ISO stands for ___

A. International Standards Organisation
B. International Software Organisation
C. Industrial Standards organisation
D. Industrial Standards organisation
Answer» B. International Software Organisation
378.

SCSI stands for ____

A. Signal Computer System Interface
B. Small Computer System Interface
C. Small Coding System Interface
D. Signal Coding System Interface
Answer» C. Small Coding System Interface
379.

Gateway

A. SCSI BUS
B. USB
C. PCI BUS
D. None of the mentioned
Answer» D. None of the mentioned
380.

The use of spooler programs or _______ Hardware allows PC operators to do the processing work at the same time a printing operation is in progress.

A. Registers
B. Memory
C. Buffer
D. CPU
Answer» D. CPU
381.

____ is used as an intermediate to extend the processor BUS

A. Bridge
B. Router
C. Connector
D. Gateway
Answer» B. Router
382.

The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is ___

A. BUS side
B. Port side
C. Hardwell side
D. Software side
Answer» C. Hardwell side
383.

User programmable terminals that combine VDT hardware with built-in microprocessor is ___

A. KIPs
B. Pc
C. Mainframe
D. Intelligent terminals
Answer» E.
384.

The parallel mode of communication is not suitable for long devices because of __

A. Timing skew
B. Memory access delay
C. Latency
D. None of the mentioned
Answer» B. Memory access delay
385.

The status flags required for data transfer is present in _

A. Device
B. Device driver
C. Interface circuit
D. None of the mentioned
Answer» D. None of the mentioned
386.

The transmission on the asynchronous BUS is also called as __

A. Switch mode transmission
B. Variabel transfer
C. Bulk transfer
D. Hand-Shake transmission
Answer» E.
387.

_____ serves as a intermediary between the device and the BUSes.

A. Interface circuits
B. Device drivers
C. Buffers
D. None of the mentioned
Answer» B. Device drivers
388.

The BUS that allows I/O,memory and Processor to coexist is ___

A. Artibuted BUS
B. Processor BUS
C. Backplane BUS
D. External BUS
Answer» D. External BUS
389.

MRDC stands for _____

A. Memory Read Enable
B. Memory Ready Command
C. Memory Re-direct Command
D. None of the mentioned
Answer» C. Memory Re-direct Command
390.

____________ signal is used as an acknowledgement signal by the slave in Multiple cycle transfers.

A. Ack signal
B. Slave ready signal
C. Master ready signal
D. Slave recieval signal
Answer» C. Master ready signal
391.

In IBM’s S360/370 systems _____ lines are used to select the I/O devices.

A. SCAN in and out
B. Connect
C. Search
D. Peripheral
Answer» B. Connect
392.

The master indicates that the address is loaded onto the BUS,by activating _____ signal.

A. MSYN
B. SSYN
C. WMFC
D. INTR
Answer» B. SSYN
393.

Which is fed into the BUS first by the initiator..?

A. Data
B. Address
C. Commands or controls
D. Address, Commands or controls
Answer» E.
394.

If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration

A. Device A
B. Device B
C. Insufficient information
D. None of the mentioned
Answer» C. Insufficient information
395.

In Distributed arbitration, the device requesting the BUS _

A. Asserts the Start arbitration signal
B. Sends an interrupt signal
C. Sends an acknowledge signal
D. None of the mentioned
Answer» B. Sends an interrupt signal
396.

How is a device selected in Distributed arbitration ?

A. By NANDing the signals passed on all the 4 lines
B. By ANDing the signals passed on all the 4 lines
C. By ORing the signals passed on all the 4 lines
D. None of the mentioned
Answer» D. None of the mentioned
397.

Distributed arbitration makes use of ____

A. BUS master
B. Processor
C. Arbitrator
D. 4-bit ID
Answer» E.
398.

The BUS busy line is used

A. To indicate the processor is busy
B. To indicate that the BUS master is busy
C. To indiacate the BUS is already allocated
D. None of the mentioned
Answer» D. None of the mentioned
399.

After the device completes its operation _____ assumes the control of the BUS.

A. Another device
B. Processor
C. Controller
D. None of the mentioned
Answer» C. Controller
400.

The BUS busy line is made of __

A. Open-drain circuit
B. Open-collector circuit
C. EX-Or circuit
D. Nor circuit
Answer» C. EX-Or circuit