MCQOPTIONS
Saved Bookmarks
| 1. |
What is the use of assert statement in VHDL? |
| A. | To print any string |
| B. | To check the consistency and generate a message |
| C. | Cause execution of sequential statements to wait |
| D. | To check if a condition can stop the execution |
| Answer» C. Cause execution of sequential statements to wait | |