Refer to the VHDL code given below, which is the legal assignment sta

1.	Refer to the VHDL code given below, which is the legal assignment statement?
A.	y <= (1 => ‘1’, OTHERS => ’0’);
B.	y := “0100”;
C.	y => “0100”;
D.	y => x;View Answer
Answer» B. y := “0100”;

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