For an input pulse train of clock period T, the delay produced by an n stage shift register

For an input pulse train of clock period T, the delay produced by an n

1.	For an input pulse train of clock period T, the delay produced by an n stage shift register
A.	(n 1) T
B.	nT
C.	(n + 1) T
D.	2nT
Answer» C. (n + 1) T