A standard CMOS inverter is designed with equal rise and fall times (βn = βp). If the width of the P MOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin (NMH) ?

NML decreases and NMH increases

NML increases and NMH decreases

A standard CMOS inverter is designed with equal rise and fall times (�

1.	A standard CMOS inverter is designed with equal rise and fall times (βn = βp). If the width of the P MOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin (NMH) ?
A.	NML increases and NMH decreases
B.	NML decreases and NMH increases
C.	Both NML and NMH increase
D.	No change in the noise margins
Answer» B. NML decreases and NMH increases

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A standard CMOS inverter is designed with equal rise and fall times (βn = βp). If the width of the P MOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NML) and the HIGH noise margin (NMH) ?

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