MCQOPTIONS
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MCQOPTIONS
This section includes 10 Mcqs, each offering curated multiple-choice questions to sharpen your Electronic Engineering (MCQ) questions & answers knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
In synthesis flow, the flattening process generates a flat signal representation of _____levels.A. ANDB. ORC. NOTD. EX-OR |
| A. | A & B |
| B. | C & D |
| C. | A & C |
| D. | B & D |
| Answer» B. C & D | |
| 2. |
Simple Programmable Logic Devices (SPLDs) are also regarded as _____________. |
| A. | Programmable Array Logic (PAL) |
| B. | Generic Array Logic (GAL) |
| C. | Programmable Logic Array (PLA) |
| D. | All of the above |
| Answer» E. | |
| 3. |
The output of sequential circuit is regarded as a function of time sequence of __________.A. InputsB. OutputsC. Internal StatesD. External States |
| A. | A & D |
| B. | A & C |
| C. | B & D |
| D. | B & C |
| Answer» C. B & D | |
| 4. |
An Antifuse programming technology is predomi tly associated with _____. |
| A. | SPLDs |
| B. | FPGAs |
| C. | CPLDs |
| D. | All of the above |
| Answer» C. CPLDs | |
| 5. |
Which programming technology/ies is/are predomi tly associated with SPLDs and CPLDs? |
| A. | EPROM |
| B. | EEPROM |
| C. | FLASH |
| D. | All of the above |
| Answer» E. | |
| 6. |
Maze routing is used to determine the _______path for a single wire between a set of points, if any path exists. |
| A. | Shortest |
| B. | Average |
| C. | Longest |
| D. | None of the above |
| Answer» B. Average | |
| 7. |
Stuck open (off) fault occur/s due to _________ |
| A. | An incomplete contact (open) of source to drain node |
| B. | Large separation of drain or source diffusion from the gate |
| C. | Both a and b |
| D. | None of the above |
| Answer» D. None of the above | |
| 8. |
In MOS switch, clock feedthrough effect is also known as __________.A. charge injectionB. charge feedthroughC. charge carrierD. charge ejaculation |
| A. | A & B |
| B. | B & C |
| C. | C & D |
| D. | B & D |
| Answer» B. B & C | |
| 9. |
In high noise margin (NM), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate. |
| A. | Driven |
| B. | Receiving |
| C. | Both a and b |
| D. | None of the above |
| Answer» C. Both a and b | |
| 10. |
In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & V yielding _____ output. |
| A. | 1 |
| B. | 0 |
| C. | Both a and b |
| D. | None of the above |
| Answer» B. 0 | |