Explore topic-wise MCQs in Digital Circuits.

This section includes 27 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.

1.

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

A. The clock pulse is LOW
B. The clock pulse is HIGH
C. The clock pulse transitions from LOW to HIGH
D. The clock pulse transitions from HIGH to LOW
Answer» D. The clock pulse transitions from HIGH to LOW
Discussion
2.

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________

A. Constantly LOW
B. Constantly HIGH
C. A 20 kHz square wave
D. A 10 kHz square wave
Answer» E.
Discussion
3.

What does the direct line on the clock input of a J-K flip-flop mean?

A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer» E.
Discussion
4.

What does the circle on the clock input of a J-K flip-flop mean?

A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer» D. Level triggered
Discussion
5.

What does the triangle on the clock input of a J-K flip-flop mean?

A. Level enabled
B. Edge triggered
C. Both Level enabled & Edge triggered
D. Level triggered
Answer» C. Both Level enabled & Edge triggered
Discussion
6.

The flip-flops which has not any invalid states are _____________

A. S-R, J-K, D
B. S-R, J-K, T
C. J-K, D, S-R
D. J-K, D, T
Answer» E.
Discussion
7.

Both the J-K & the T flip-flop are derived from the basic _____________

A. S-R flip-flop
B. S-R latch
C. D latch
D. D flip-flop
Answer» C. D latch
Discussion
8.

The S-R latch composed of NAND gates is called an active low circuit because _____________

A. It is only activated by a positive level trigger
B. It is only activated by a negative level trigger
C. It is only activated by either a positive or negative level trigger
D. It is only activated by sinusoidal trigger
Answer» C. It is only activated by either a positive or negative level trigger
Discussion
9.

The flip-flop is only activated by _____________

A. Positive edge trigger
B. Negative edge trigger
C. Either positive or Negative edge trigger
D. Sinusoidal trigger
Answer» D. Sinusoidal trigger
Discussion
10.

How many stable states combinational circuits have?

A. 3
B. 4
C. 2
D. 5
Answer» D. 5
Discussion
11.

The only difference between a combinational circuit and a flip-flop is that _____________

A. The flip-flop requires previous state
B. The flip-flop requires next state
C. The flip-flop requires a clock pulse
D. The flip-flop depends on the past as well as present states
Answer» D. The flip-flop depends on the past as well as present states
Discussion
12.

In J-K flip-flop, the function K=J is used to realize _____________

A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. S-K flip-flop
Answer» D. S-K flip-flop
Discussion
13.

In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________

A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. S-K flip-flop
Answer» D. S-K flip-flop
Discussion
14.

The characteristic equation of J-K flip-flop is ______________

A. Q(n+1)=JQ(n)+K’Q(n)
B. Q(n+1)=J’Q(n)+KQ'(n)
C. Q(n+1)=JQ'(n)+KQ(n)
D. Q(n+1)=JQ'(n)+K’Q(n)
Answer» E.
Discussion
15.

THE_FLIP-FLOPS_WHICH_HAS_NOT_ANY_INVALID_STATES_ARE?$

A. S-R, J-K, D
B. S-R, J-K, T
C. J-K, D, S-R
D. J-K, D, T
Answer» E.
Discussion
16.

What does the direct line on the clock input of a J-K flip-flop mean?$

A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer» E.
Discussion
17.

What_does_the_triangle_on_the_clock_input_of_a_J-K_flip-flop_mean?$

A. Level enabled
B. Edge triggered
C. Both a & b
D. Level triggered
Answer» C. Both a & b
Discussion
18.

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is

A. Constantly LOW
B. Constantly HIGH
C. A 20 kHz square wave
D. A 10 kHz square wave
Answer» E.
Discussion
19.

What does the half circle on the clock input of a J-K flip-flop mean?

A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer» E.
Discussion
20.

Both the J-K & the T flip-flop are derived from the basi?

A. S-R flip-flop
B. S-R latch
C. D latch
D. D flip-flop
Answer» C. D latch
Discussion
21.

The S-R latch composed of NAND gates is called an active low circuit because

A. It is only activated by a positive level trigger
B. It is only activated by a negative level trigger
C. It is only activated by either a positive or negative level trigger
D. None of the Mentioned
Answer» C. It is only activated by either a positive or negative level trigger
Discussion
22.

The flip-flop is only activated by

A. Positive edge trigger
B. Negative edge trigger
C. Either positive or Negative edge trigger
D. None of the Mentioned
Answer» D. None of the Mentioned
Discussion
23.

How many stable states a combinational circuits have?

A. 3
B. 4
C. 2
D. 5
Answer» D. 5
Discussion
24.

The only difference between a combinational circuit and a flip-flop is that

A. The flip-flop requires previous state
B. The flip-flop requires next state
C. The flip-flop requires a clock pulse
D. None of the Mentioned
Answer» D. None of the Mentioned
Discussion
25.

In J-K flip-flop , the function K=J is used to realize

A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. None of the Mentioned
Answer» D. None of the Mentioned
Discussion
26.

In a J-K flip-flop, if J=K the resulting flip-flop is referred to as

A. D flip-flop
B. T flip-flop
C. S-R flip-flop
D. None of the Mentioned
Answer» D. None of the Mentioned
Discussion
27.

The characteristic equation of J-K flip-flop is

A. Q(n+1)=JQ(n)+K’Q(n)
B. Q(n+1)=J’Q(n)+KQ'(n)
C. Q(n+1)=JQ'(n)+KQ(n)
D. None of the Mentioned
Answer» B. Q(n+1)=J‚Äö√Ñ√∂‚àö√ë‚àö¬•Q(n)+KQ'(n)
Discussion