MCQOPTIONS
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MCQOPTIONS
This section includes 13 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
THE_FLOATING_POINT_MULTIPLIER_SEGMENT_PERFORMS_FLOATING_POINT_MULTIPLICATION_IN?$ |
| A. | single precision |
| B. | double precision |
| C. | extended precision |
| D. | all of the mentioned |
| Answer» E. | |
| 2. |
The floating point rounder segment performs rounding off operation at$ |
| A. | after write back stage |
| B. | before write back stage |
| C. | before arithmetic operations |
| D. | none of the mentioned |
| Answer» C. before arithmetic operations | |
| 3. |
The_instruction_or_segment_that_executes_the_floating_point_square_root_instructions_is$ |
| A. | floating point square root segment |
| B. | floating point division and square root segment |
| C. | floating point divider segment |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 4. |
The mechanism that determines whether a floating point operation will be executed without creating any exception is |
| A. | Multiple Instruction Issue |
| B. | Multiple Exception Issue |
| C. | Safe Instruction Recognition |
| D. | Safe Exception Recognition |
| Answer» D. Safe Exception Recognition | |
| 5. |
Which of the following is a floating point exception that is generated in case of integer arithmetic? |
| A. | divide by zero |
| B. | overflow |
| C. | denormal operand |
| D. | all of the mentioned |
| Answer» E. | |
| 6. |
The FPU (Floating Point Unit) writes the results to the floating point register file i? |
| A. | X1 execution state |
| B. | X2 execution state |
| C. | write back stage |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 7. |
In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from |
| A. | floating point unit |
| B. | instruction cache |
| C. | floating point register file or data cache |
| D. | floating point register file or instruction cache |
| Answer» D. floating point register file or instruction cache | |
| 8. |
The feature of separated caches is |
| A. | supports the superscalar organization |
| B. | high bandwidth |
| C. | low hit ratio |
| D. | all of the mentioned |
| Answer» E. | |
| 9. |
The stage in which the CPU generates an address for data memory references in this stage is |
| A. | prefetch stage |
| B. | D1 (first decode) stage |
| C. | D2 (second decode) stage |
| D. | execution stage |
| Answer» D. execution stage | |
| 10. |
In the execution stage the function performed is |
| A. | CPU accesses data cache |
| B. | executes arithmetic/logic computations |
| C. | executes floating point operations in execution unit |
| D. | all of the mentioned |
| Answer» E. | |
| 11. |
The fifth stage of pipeline is also known as |
| A. | read back stage |
| B. | read forward stage |
| C. | write back stage |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| 12. |
The CPU decodes the instructions and generates control words in |
| A. | Prefetch stage |
| B. | D1 (first decode) stage |
| C. | D2 (second decode) stage |
| D. | Final stage |
| Answer» C. D2 (second decode) stage | |
| 13. |
The stage in which the CPU fetches the instructions from the instruction cache in superscalar organization is |
| A. | Prefetch stage |
| B. | D1 (first decode) stage |
| C. | D2 (second decode) stage |
| D. | Final stage |
| Answer» B. D1 (first decode) stage | |