MCQOPTIONS
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MCQOPTIONS
This section includes 4 Mcqs, each offering curated multiple-choice questions to sharpen your Microprocessors knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The on-chip cache can be flushed using external hardware using |
| A. | FLUSH pin |
| B. | TERMINATE pin |
| C. | FLOW pin |
| D. | Pin FLUSH# or using software |
| Answer» E. | |
| 2. |
The on-chip cache is controlled by |
| A. | Cache disable(CD) |
| B. | No write through(NW) |
| C. | Cache disable and No write through |
| D. | None of the mentioned |
| Answer» D. None of the mentioned | |
| 3. |
The on-chip cache is used for storing |
| A. | addresses of data |
| B. | opcodes and data |
| C. | data and their addresses |
| D. | opcodes and their addresses |
| Answer» C. data and their addresses | |
| 4. |
In Little Endian data format, the data is stored as |
| A. | MSB is stored at lower memory address and LSB at higher memory address |
| B. | LSB is stored at lower memory address and MSB at higher memory address |
| C. | MSB is stored at general purpose registers |
| D. | LSB is stored at general purpose registers |
| Answer» C. MSB is stored at general purpose registers | |