MCQOPTIONS
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MCQOPTIONS
This section includes 15 Mcqs, each offering curated multiple-choice questions to sharpen your Computer Organization knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
IN_IA-32_ARCHITECTURE_ALONG_WITH_THE_GENERAL_FLAGS,_THE_OTHER_CONDITIONAL_FLAGS_PROVIDED_ARE______?$ |
| A. | IOPL |
| B. | IF |
| C. | TF |
| D. | All of the mentioned |
| Answer» E. | |
| 2. |
The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit.$ |
| A. | True |
| B. | False |
| Answer» B. False | |
| 3. |
The_register_used_to_serve_as_PC_is_called_as________$ |
| A. | Indirection register |
| B. | Instruction pointer |
| C. | R-32 |
| D. | None of the mentioned |
| Answer» C. R-32 | |
| 4. |
The LEA mnemonic is used to __________ |
| A. | Load the effective address of an instruction |
| B. | Load the values of operands onto an accumulator |
| C. | declare the values as global constants |
| D. | Store the outcome of the operation at a memory location |
| Answer» B. Load the values of operands onto an accumulator | |
| 5. |
The instruction JG loop does ______ |
| A. | jumps to the memory location loop if the result of the most recent arithmetic op is even |
| B. | jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 |
| C. | jumps to the memory location loop if the test condition is satisfied with the value of loop |
| D. | none of the mentioned |
| Answer» C. jumps to the memory location loop if the test condition is satisfied with the value of loop | |
| 6. |
The instruction, ADD R1, R2, R3 is decoded as _______ |
| A. | R1<-[R1]+[R2]+[R3]. |
| B. | R3<-[R1]+[R2]. |
| C. | R3<-[R1]+[R2]+[R3]. |
| D. | R1<-[R2]+[R3]. |
| Answer» E. | |
| 7. |
The_Bit_extension_of_the_register_is_denoted_with_the_help_of______symbol. |
| A. | $ |
| B. | ` |
| C. | E |
| D. | ~ |
| Answer» D. ~ | |
| 8. |
IOPL stands for _______? |
| A. | Input/Output Privilege level |
| B. | Input Output Process Link |
| C. | Internal Output Process Link |
| D. | Internal Offset Privilege Level |
| Answer» B. Input Output Process Link | |
| 9. |
The PC is incorporated with the help of general purpose registers. |
| A. | True |
| B. | False |
| Answer» C. | |
| 10. |
The IA-32 architecture associates different parts of memory called ____ with different usages. |
| A. | Frames |
| B. | Pages |
| C. | Tables |
| D. | Segments |
| Answer» E. | |
| 11. |
The size of the floating registers can be extended upto _____ |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» D. 64 bit | |
| 12. |
The Floating point registers of IA-32 can operate on operands up to _____ |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» E. | |
| 13. |
The floating point numbers are stored in general purpose register in IA-32. |
| A. | True |
| B. | False |
| Answer» C. | |
| 14. |
The addressing method used in IA-32 is ______ |
| A. | Little Endian |
| B. | Big Endian |
| C. | X-Little Endian |
| D. | Both Little and Big Endian |
| Answer» B. Big Endian | |
| 15. |
The address space of the IA-32 is ____ |
| A. | 2<sup>16</sup> |
| B. | 2<sup>32</sup> |
| C. | 2<sup>64</sup> |
| D. | 2<sup>8</sup> |
| Answer» C. 2<sup>64</sup> | |