MCQOPTIONS
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MCQOPTIONS
This section includes 6 Mcqs, each offering curated multiple-choice questions to sharpen your Vhdl knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
A parity generator is a combinational circuit and is designed by using a combinational process. |
| A. | True |
| B. | False |
| Answer» B. False | |
| 2. |
In the combinational process, the use of output signal in the sensitivity list is illegal. |
| A. | True |
| B. | False |
| Answer» C. | |
| 3. |
In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the following is a correct process statement? |
| A. | PROCESS(d) |
| B. | PROCESS(d(0), d(1), s) |
| C. | PROCESS(d(0), d(1)) |
| D. | PROCESS(d, s, y) |
| Answer» B. PROCESS(d(0), d(1), s) | |
| 4. |
A package is designed called mux4to1_package, in which a component called mux4to1 is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using the same component only, how many times he needs to use the PORT MAP statement? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» E. | |
| 5. |
If only two bit vectors are allowed to use in the VHDL code, then how many number of MUX will be required to implement 4 to 1 MUX? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 6. |
The process statement used in combinational circuits is called ______ process. |
| A. | Combinational |
| B. | Clocked |
| C. | Unclocked |
| D. | Sequential |
| Answer» B. Clocked | |