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				This section includes 6 Mcqs, each offering curated multiple-choice questions to sharpen your Power Electronics Question and Answers Single-Phase HW AC-DC-1 knowledge and support exam preparation. Choose a topic below to get started.
| 1. | 
                                    A single-phase half-wave thyristor circuit with R load is triggered at an angle of = 0 . As such, the maximum value of the average output voltage would be given byConsider Vs = Vm sin t. | 
                            
| A. | Vm | 
| B. | 2Vm/ | 
| C. | Vm/ | 
| D. | Vm/ | 
| Answer» D. Vm/ | |
| 2. | 
                                    For a single phase thyristor circuit with R load & firing angle , the conduction angle can be given by | 
                            
| A. | + | 
| B. | 2 + | 
| C. | - | 
| D. | |
| Answer» D. | |
| 3. | 
                                    In a single phase half-wave thyristor circuit with R load & Vs=Vm sin t, the maximum value of the load current can be given by | 
                            
| A. | 2Vm/R | 
| B. | Vs/R | 
| C. | Vm/2 | 
| D. | Vs/2 | 
| Answer» D. Vs/2 | |
| 4. | 
                                    In the method of phase control, the phase relationship between ___ & ___ is controlled by varying the firing angle | 
                            
| A. | supply current, supply voltage | 
| B. | end of the load current, end of the load voltage | 
| C. | start of the load current, start of the load voltage | 
| D. | load current, load voltage | 
| Answer» D. load current, load voltage | |
| 5. | 
                                    The average output voltage is maximum when SCR is triggered at t = | 
                            
| A. | |
| B. | 0 | 
| C. | /2 | 
| D. | /4 | 
| Answer» C. /2 | |
| 6. | 
                                    A voltage source Vs = Vm sin t is connected in series with a resistance R and an SCR. At some firing angle delay of a positive gate pulse is applied to the SCR which turns on the SCR. Considering ideal conditions, at the instant the voltage at the resistor terminals Vo | 
                            
| A. | falls to zero | 
| B. | falls to Vm sin | 
| C. | rises to Vm sin | 
| D. | rises to Vm sin t | 
| Answer» D. rises to Vm sin t | |