MCQOPTIONS
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MCQOPTIONS
This section includes 406 Mcqs, each offering curated multiple-choice questions to sharpen your Graduate Aptitude Test (GATE) knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Consider the following circuit. Which one of the following is true? |
| A. | f is independent of X |
| B. | f is independent of Y |
| C. | f is independent of Z |
| D. | None of X, Y, Z is redundant |
| Answer» D. None of X, Y, Z is redundant | |
| 2. |
Identify which of the following prime implicant is not valid? |
| A. | A'C'D |
| B. | A'BD |
| C. | A'BC |
| D. | BD |
| Answer» C. A'BC | |
| 3. |
The following truth table represents the Boolean function |
| A. | X |
| B. | X+Y |
| C. | XΦY |
| D. | Y |
| Answer» B. X+Y | |
| 4. |
What is the minimum number of 2 – input NAND gates are required for realizing the following function? |
| A. | 3 |
| B. | 4 |
| C. | 5 |
| D. | 6 |
| Answer» D. 6 | |
| 5. |
Consider the following circuit composed of XOR gates and non-inverting buffers. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» E. | |
| 6. |
Consider the following circuit. Except the Buffers, no gate and no connecting lead is having the delay and All inputs and outputs of gates are zero initially. Consider the timining diagram X has made. How many changes does Y undergone? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» D. 5 | |
| 7. |
The following diagram shows, which addressing mode? |
| A. | Immediate addressing mode |
| B. | Indirect addressing mode |
| C. | Extended addressing mode |
| D. | None of the above |
| Answer» D. None of the above | |
| 8. |
Consider on (n+k) bit instruction with a k-bit opcode and single n-bit address. Then this instruction allows…………….. Operations and …………… addressable memory cells.? |
| A. | A |
| B. | B |
| C. | C |
| D. | D |
| Answer» D. D | |
| 9. |
Consider the combinational decoder, then find out the expression for the function. |
| A. | x+y |
| B. | xy’ |
| C. | x’+y |
| D. | None of these |
| Answer» D. None of these | |
| 10. |
Consider the following state table. What will be the minimum length of input required to table the machine into state ‘C’? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 11. |
The Boolean expression for the output f of the multiplex shown below is |
| A. | A |
| B. | B |
| C. | C |
| D. | D |
| Answer» C. C | |
| 12. |
Using the select lines; what is the function represented by the following multiplexer? |
| A. | C |
| B. | C' |
| C. | A, B |
| D. | A, B, C |
| Answer» B. C' | |
| 13. |
Consider the combination of multiplexers with inputs A, B and select lines A, C. What is the expression can be obtained from the combinational circuit? |
| A. | AC+BC |
| B. | AB+BC |
| C. | AB+BC+CA |
| D. | none of the above |
| Answer» B. AB+BC | |
| 14. |
Consider the following circuit. The flip – flops are positive edge triggered D FFs. Each state is designated as a two bit string Q₀ Q₁. Let the initial state be 00. The state transition sequence is |
| A. | A |
| B. | B |
| C. | C |
| D. | D |
| Answer» E. | |
| 15. |
Consider the following multiplexer. Using the select lines, what is the function represented by the mux? |
| A. | X+Y+Z’ |
| B. | XYZ’ |
| C. | XY+YZ+ZX |
| D. | None of these |
| Answer» C. XY+YZ+ZX | |
| 16. |
Consider the decoder with 3 inputs A, B, C. Find out the function from the decoder circuit and the function is free from which variable? |
| A. | A |
| B. | B |
| C. | C |
| D. | Depend on all variables |
| Answer» C. C | |
| 17. |
What is the value of counter after 3 clock pulses? |
| A. | 0 0 0 |
| B. | 0 1 1 |
| C. | 1 0 1 |
| D. | 1 1 0 |
| Answer» E. | |
| 18. |
Consider the following circuit involving a positive edge triggered DFF. Consider the following timing diagram. Let Aᵢ |
| A. | A₀A₁A′₁A₃A₄ |
| B. | A₀A₁A′₂A₃A₄ |
| C. | A₁A₂A′₂A₃A₄ |
| D. | A₁A'₂A₃A₄A′₅ |
| Answer» B. A₀A₁A′₂A₃A₄ | |
| 19. |
In the sequential circuit shown below, If the initial value of the output Q₁Q₀ is 00, what are the next four values of Q₁Q₀ ? |
| A. | 11, 10, 01, 00 |
| B. | 10, 11, 01, 00 |
| C. | 10, 00, 01, 11 |
| D. | 11, 10, 00, 01 |
| Answer» B. 10, 11, 01, 00 | |
| 20. |
What is the equivalent decimal representation for the following radix representation? |
| A. | (22.56)₁₀ |
| B. | (32.56)₁₀ |
| C. | (28.5625)₁₀ |
| D. | (38.5625)₁₀ |
| Answer» D. (38.5625)₁₀ | |
| 21. |
In a two-level memory hierarchy, the access time of the memory is 12 nanoseconds and the access time of the main memory is 1.5 microseconds. The hit ratio is 0.98. What is the average access time of the two-level memory system? |
| A. | 13.5n sec |
| B. | 42n sec |
| C. | 7.56n sec |
| D. | 76n sec |
| Answer» E. | |
| 22. |
The range of integers that can be represented by an n – bit 2's complement number system is |
| A. | – 2ⁿ⁻¹ to (2ⁿ⁻¹ -1) |
| B. | – (2ⁿ⁻¹ -1) to (2ⁿ⁻¹ -1) |
| C. | – 2ⁿ⁻¹ to 2ⁿ⁻¹ |
| D. | – (2ⁿ⁻¹ +1) to (2ⁿ⁻¹ -1) |
| Answer» B. – (2ⁿ⁻¹ -1) to (2ⁿ⁻¹ -1) | |
| 23. |
Which of the following statement is FALSE regarding functionally completeness, (FC). |
| A. | A Boolean function is said to be FC if it realizes all the basic operations (AND, OR, NOT) |
| B. | A function can be FC if it reduces to another function i.e.., already known as FC |
| C. | All the universal operations are FC |
| D. | None of the above |
| Answer» E. | |
| 24. |
Consider the following organization of main memory and cache memory. |
| A. | 5 bits |
| B. | 6 bits |
| C. | 7 bits |
| D. | 8 bits |
| Answer» E. | |
| 25. |
If P,Q,R are boolean variables, then (P+Q’)(PQ’+PR)(P’R’+Q’) simplifies to |
| A. | PQ’ |
| B. | PR’ |
| C. | PQ’ + R |
| D. | PR’ + Q |
| Answer» B. PR’ | |
| 26. |
Find x & y values if the following equality is valid. |
| A. | 43 |
| B. | 34 |
| C. | 45 |
| D. | 54 |
| Answer» B. 34 | |
| 27. |
In a fully associative cache memory consisting of 256 cache lines of 16 bytes each, a tag field is of 14 bits. Determine the size of cache memory and main memory. |
| A. | 2KB and 128 KB |
| B. | 4kB and 256KB |
| C. | 8KB and 1MB |
| D. | None of the above |
| Answer» C. 8KB and 1MB | |
| 28. |
An instruction cycle refers to |
| A. | Fetching an instruction |
| B. | Clock speed |
| C. | Fetching, decoding, and executing an instruction |
| D. | Executing an instruction |
| Answer» D. Executing an instruction | |
| 29. |
ID catching system, the memory reference made in any short time integral tends to use only a small fraction of the total memory? |
| A. | Checker boarding |
| B. | Locality principle |
| C. | Memory interleaving |
| D. | None of the above |
| Answer» C. Memory interleaving | |
| 30. |
P is a 16 – bit signed integer. The 2’s complement representation of P is (F87B)₁₆. The 2’s complement representation of 8 * p is |
| A. | (C3D8)₁₆ |
| B. | (187B)₁₆ |
| C. | (F878)₁₆ |
| D. | (987B)₁₆ |
| Answer» B. (187B)₁₆ | |
| 31. |
The register which holds the address of the locating to or from which data are to be transferred is known as |
| A. | Index register |
| B. | Instruction register |
| C. | Memory address register |
| D. | Memory data register |
| Answer» D. Memory data register | |
| 32. |
Which of the following data transfer modes takes relatively more time? |
| A. | DMA |
| B. | Interrupt initiated I/O |
| C. | Programmed I/O |
| D. | Isolated I/O |
| Answer» D. Isolated I/O | |
| 33. |
Assembler directives represent……………… |
| A. | Only 1 |
| B. | only 2 |
| C. | Both 1 and 2 |
| D. | Neither 1 nor 2 |
| Answer» E. | |
| 34. |
Microinstruction length is determined by ……………….. |
| A. | 1 and 2 |
| B. | 2 and 3 |
| C. | 1 and 3 |
| D. | All of the above |
| Answer» E. | |
| 35. |
The word length of a CPU is defined as |
| A. | The maximum addressable memory size |
| B. | The Width of a CPU register |
| C. | The width of the address bus |
| D. | The number of general purpose CPU registers |
| Answer» C. The width of the address bus | |
| 36. |
The CPU initializes the DMA by sending ……… |
| A. | The starting address of the memory blocks where data is available or where data is to be stared |
| B. | The word count |
| C. | Control for mode and start the transfer |
| D. | All of the above |
| Answer» E. | |
| 37. |
Consider three IP networks A, B and C. Host HA in network A sends messages each containing 180 bytes of application data to a host HC in network C. The TCP layer prefixes a 20 byte header to the message. This passes through an intermediate network B. The maximum packet size, including 20 byte IP header, in each network is A : 1000 bytes B : 100 bytes C : 1000 bytes The network A and B are connected through a 1 Mbps link, while B and C are connected by a 512 Kbps link (bps = bits per second).What is the rate at which application data is transferred to host HC? Ignore errors, acknowledgements, and other overheads. |
| A. | 325.5 Kbps |
| B. | 354.5 Kbps |
| C. | 409.6 Kbps |
| D. | 512.0 Kbps |
| Answer» C. 409.6 Kbps | |
| 38. |
Which one of the following statements is FALSE? |
| A. | HTTP runs over TCP |
| B. | HTTP describes the structure of web pages |
| C. | HTTP allows information to be stored in a URL |
| D. | HTTP can be used to test the validity of a hypertext link |
| Answer» C. HTTP allows information to be stored in a URL | |
| 39. |
Consider three IP networks A, B and C. Host HA in network A sends messages each containing 180 bytes of application data to a host HC in network C. The TCP layer prefixes a 20 byte header to the message. This passes through an intermediate network B. The maximum packet size, including 20 byte IP header, in each network is A : 1000 bytes B : 100 bytes C : 1000 bytes The network A and B are connected through a 1 Mbps link, while B and C are connected by a 512 Kbps link (bps = bits per second). Assuming that the packets are correctly delivered, how many bytes, including headers, are delivered to the IP layer at the destination for one application message, in the best case ? Consider only data packets. |
| A. | 200 |
| B. | 220 |
| C. | 240 |
| D. | 260 |
| Answer» E. | |
| 40. |
In a sliding window ARQ scheme, the transmitter's window size is N and the receiver's window size is M. The minimum number of distinct sequence numbers required to ensure correct operation of the ARQ scheme is |
| A. | min (M, N) |
| B. | max (M, N) |
| C. | M + N |
| D. | MN |
| Answer» D. MN | |
| 41. |
Which of the following protocol is called as byte-oriented protocol? |
| A. | Sliding Window Protocol |
| B. | TCP |
| C. | UDP |
| D. | HDLC |
| Answer» C. UDP | |
| 42. |
A serial transmission Ti uses 8 information bits, 2 start bits, 1 stop bit and 1 parity bit for each character. A synchronous transmission T2 uses 3 eight bit sync characters followed by 30 eight bit information characters. If the bit rate is 1200 bits/second in both cases, what are the transfer rates of Ti and T2? |
| A. | 100 characters/sec, 153 characters/sec |
| B. | 80 characters/sec, 136 characters/sec |
| C. | 100 characters/sec, 136 characters/sec |
| D. | 80 characters/sec, 153 characters/sec |
| Answer» D. 80 characters/sec, 153 characters/sec | |
| 43. |
Which of the following is false: |
| A. | Digital signature is used to verify that a message is authentic |
| B. | Digital certificate is issued by a third party |
| C. | Digital certificate ensures integrity of the message |
| D. | Digital signature ensures non-repudiation |
| Answer» D. Digital signature ensures non-repudiation | |
| 44. |
If syn = 0 and ack = 1, it indicates |
| A. | Open connection packet |
| B. | Open connection ack |
| C. | Data packet |
| D. | None of these |
| Answer» D. None of these | |
| 45. |
Which one of the following can be used on the IP network to monitor a router? |
| A. | SNMP |
| B. | SMTP |
| C. | SGCP |
| D. | SNPP |
| Answer» B. SMTP | |
| 46. |
In Go–back 3 flow control protocol every 6th packet is lost. If we have to send 11 packets. How many transmissions will be needed ? |
| A. | 10 |
| B. | 17 |
| C. | 12 |
| D. | 9 |
| Answer» C. 12 | |
| 47. |
Choose the best matching between Group 1 and Group 2. Group-1 Group-2 P. Data link 1. Ensures reliable transport of data over a physical point-to-point link Q. Network layer 2. Encoder/decodes data for physical transmission R. Transport layer 3. Allows end-to-end communication between two processes 4. Routes data from one network node to the next |
| A. | P-1, Q-4, R-3 |
| B. | P-2, Q-4, R-1 |
| C. | P-2, Q-3, R-1 |
| D. | P-1, Q-3, R-2 |
| Answer» B. P-2, Q-4, R-1 | |
| 48. |
In a ................................attack, an intruder comes between two communicating parties, Intercepting and replying to their messages. |
| A. | Return |
| B. | man – in – the middle |
| C. | Replay |
| D. | Bucket – bridge |
| Answer» C. Replay | |
| 49. |
Which one of the following statement about email is false? |
| A. | Communication takes place at the convenience of both the sender and the receiver |
| B. | Messages can be Include text, graphics audio and video |
| C. | A historical record of messages can be kept |
| D. | Files can be attached to messages |
| Answer» B. Messages can be Include text, graphics audio and video | |
| 50. |
A firewall is to be configured to allow hosts in a private network to freely open TCP connections and send packets on open connections. However, it will only allow external hosts to send packets on existing open TCP connections or connections that are being opened (by internal hosts) but not allow them to open TCP connections to hosts in the private network. To achieve this the minimum capability of the firewall should be that of |
| A. | A combinational circuit |
| B. | A finite automaton |
| C. | A pushdown automaton with one stack |
| D. | A pushdown automaton with two stacks |
| Answer» E. | |