MCQOPTIONS
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MCQOPTIONS
This section includes 7 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________ |
| A. | 1 kHz |
| B. | 2 kHz |
| C. | 4 kHz |
| D. | 16 kHz |
| Answer» C. 4 kHz | |
| 2. |
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________ |
| A. | 00 |
| B. | 11 |
| C. | 01 |
| D. | 10 |
| Answer» B. 11 | |
| 3. |
In J-K flip-flop, no change condition appears when ___________ |
| A. | J = 1, K = 1 |
| B. | J = 1, K = 0 |
| C. | J = 0, K = 1 |
| D. | J = 0, K = 0 |
| Answer» E. | |
| 4. |
The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________ |
| A. | Parity error checking |
| B. | Ones catching |
| C. | Digital discrimination |
| D. | Digital filtering |
| Answer» C. Digital discrimination | |
| 5. |
A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________ |
| A. | Two AND gates |
| B. | Two NAND gates |
| C. | Two NOT gates |
| D. | Two OR gates |
| Answer» B. Two NAND gates | |
| 6. |
The characteristic of J-K flip-flop is similar to _____________ |
| A. | S-R flip-flop |
| B. | D flip-flop |
| C. | T flip-flop |
| D. | Gated T flip-flop |
| Answer» B. D flip-flop | |
| 7. |
Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs? |
| A. | Gated JK-latch |
| B. | Gated SR-latch |
| C. | Gated T-latch |
| D. | Gated D-latch |
| Answer» E. | |