MCQOPTIONS
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MCQOPTIONS
This section includes 9 Mcqs, each offering curated multiple-choice questions to sharpen your Digital Circuits knowledge and support exam preparation. Choose a topic below to get started.
| 1. |
The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________ |
| A. | Edge-detection circuit |
| B. | NOR latch |
| C. | NAND latch |
| D. | Pulse-steering circuit |
| Answer» B. NOR latch | |
| 2. |
One example of the use of an S-R flip-flop is as ____________ |
| A. | Racer |
| B. | Stable oscillator |
| C. | Binary storage register |
| D. | Transition pulse generator |
| Answer» D. Transition pulse generator | |
| 3. |
The S-R flip flop consist of ____________ |
| A. | 4 AND gates |
| B. | Two additional AND gates |
| C. | An additional clock input |
| D. | 3 AND gates |
| Answer» C. An additional clock input | |
| 4. |
The difference between a flip-flop & latch is ____________ |
| A. | Both are same |
| B. | Flip-flop consist of an extra output |
| C. | Latches has one input but flip-flop has two |
| D. | Latch has two inputs but flip-flop has one |
| Answer» D. Latch has two inputs but flip-flop has one | |
| 5. |
The characteristic equation of S-R latch is ____________ |
| A. | Q(n+1) = (S + Q(n))R |
| B. | Q(n+1) = SR + Q(n)R |
| C. | Q(n+1) = S R + Q(n)R |
| D. | Q(n+1) = S R + Q'(n)R |
| Answer» B. Q(n+1) = SR + Q(n)R | |
| 6. |
One major difference between a NAND based S -R latch & a NOR based S-R latch is ____________ |
| A. | The inputs of NOR latch are 0 but 1 for NAND latch |
| B. | The inputs of NOR latch are 1 but 0 for NAND latch |
| C. | The output of NAND latch becomes set if S =0 & R =1 and vice versa for NOR latch |
| D. | The output of NOR latch is 1 but 0 for NAND latch |
| Answer» B. The inputs of NOR latch are 1 but 0 for NAND latch | |
| 7. |
A NAND based S -R latch can be converted into S-R latch by placing ____________ |
| A. | A D latch at each of its input |
| B. | An inverter at each of its input |
| C. | It can never be converted |
| D. | Both a D latch and an inverter at its input |
| Answer» E. | |
| 8. |
In a NAND based S -R latch, if S =1 & R =1 then the state of the latch is ____________ |
| A. | No change |
| B. | Set |
| C. | Reset |
| D. | Forbidden |
| Answer» B. Set | |
| 9. |
What is an ambiguous condition in a NAND based S -R latch? |
| A. | S =0, R =1 |
| B. | S =1, R =0 |
| C. | S =1, R =1 |
| D. | S =0, R =0 |
| Answer» E. | |